1b7511552SDhaval ShahLogicoreIP designed compatible with Xilinx ZYNQ family. 2b7511552SDhaval Shah------------------------------------------------------- 3b7511552SDhaval Shah 4b7511552SDhaval ShahGeneral concept 5b7511552SDhaval Shah--------------- 6b7511552SDhaval Shah 7b7511552SDhaval ShahLogicoreIP design to provide the isolation between processing system 8b7511552SDhaval Shahand programmable logic. Also provides the list of register set to configure 9b7511552SDhaval Shahthe frequency. 10b7511552SDhaval Shah 11b7511552SDhaval ShahRequired properties: 12b7511552SDhaval Shah- compatible: shall be one of: 13b7511552SDhaval Shah "xlnx,vcu" 14b7511552SDhaval Shah "xlnx,vcu-logicoreip-1.0" 15b7511552SDhaval Shah- reg, reg-names: There are two sets of registers need to provide. 16b7511552SDhaval Shah 1. vcu slcr 17b7511552SDhaval Shah 2. Logicore 18b7511552SDhaval Shah reg-names should contain name for the each register sequence. 19b7511552SDhaval Shah- clocks: phandle for aclk and pll_ref clocksource 20b7511552SDhaval Shah- clock-names: The identification string, "aclk", is always required for 21b7511552SDhaval Shah the axi clock. "pll_ref" is required for pll. 22b7511552SDhaval ShahExample: 23b7511552SDhaval Shah 24b7511552SDhaval Shah xlnx_vcu: vcu@a0040000 { 25b7511552SDhaval Shah compatible = "xlnx,vcu-logicoreip-1.0"; 26b7511552SDhaval Shah reg = <0x0 0xa0040000 0x0 0x1000>, 27b7511552SDhaval Shah <0x0 0xa0041000 0x0 0x1000>; 28b7511552SDhaval Shah reg-names = "vcu_slcr", "logicore"; 29b7511552SDhaval Shah clocks = <&si570_1>, <&clkc 71>; 30b7511552SDhaval Shah clock-names = "pll_ref", "aclk"; 31b7511552SDhaval Shah }; 32