1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Wakeup M3 IPC device
8
9maintainers:
10  - Dave Gerlach <d-gerlach@ti.com>
11  - Drew Fustini <dfustini@baylibre.com>
12
13description: |+
14  The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
15  (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
16  that cannot be controlled from the MPU, like suspend/resume and certain deep
17  C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
18  to boot the wkup_m3, it handles communication with the CM3 using IPC registers
19  present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
20  API to allow the SoC PM code to execute specific PM tasks.
21
22  Wkup M3 Device Node
23  ====================
24  A wkup_m3_ipc device node is used to represent the IPC registers within an
25  SoC.
26
27  Support for VTT Toggle with GPIO pin
28  ====================================
29  On some boards like the AM335x EVM-SK and the AM437x GP EVM, a GPIO pin is
30  connected to the enable pin on the DDR VTT regulator. This allows the
31  regulator to be disabled upon suspend and enabled upon resume. Please note
32  that the GPIO pin must be part of the GPIO0 module as only this GPIO module
33  is in the wakeup power domain.
34
35  Support for IO Isolation
36  ========================
37  On AM437x SoCs, certain pins can be forced into an alternate state when IO
38  isolation is activated. Those pins have pad control registers prefixed by
39  'CTRL_CONF_' that contain DS0 (e.g. deep sleep) configuration bits that can
40  override the pin's existing bias (pull-up/pull-down) and value (high/low) when
41  IO isolation is active.
42
43properties:
44  compatible:
45    enum:
46      - ti,am3352-wkup-m3-ipc # for AM33xx SoCs
47      - ti,am4372-wkup-m3-ipc # for AM43xx SoCs
48
49  reg:
50    description:
51      The IPC register address space to communicate with the Wakeup M3 processor
52    maxItems: 1
53
54  interrupts:
55    description: wkup_m3 interrupt that signals the MPU
56    maxItems: 1
57
58  ti,rproc:
59    $ref: /schemas/types.yaml#/definitions/phandle
60    description:
61      phandle to the wkup_m3 rproc node so the IPC driver can boot it
62
63  mboxes:
64    description:
65      phandles used by IPC framework to get correct mbox
66      channel for communication. Must point to appropriate
67      mbox_wkupm3 child node.
68    maxItems: 1
69
70  ti,vtt-gpio-pin:
71    $ref: /schemas/types.yaml#/definitions/uint32
72    description: GPIO pin connected to enable pin on VTT regulator
73
74  ti,set-io-isolation:
75    type: boolean
76    description:
77      If this property is present, then the wkup_m3_ipc driver will instruct
78      the CM3 firmware to activate IO isolation when suspending to deep sleep.
79      This can be leveraged by a board design to put other devices on the board
80      into a low power state.
81
82allOf:
83  - if:
84      properties:
85        compatible:
86          not:
87            contains:
88              const: ti,am4372-wkup-m3-ipc
89    then:
90      properties:
91        ti,set-io-isolation: false
92
93required:
94  - compatible
95  - reg
96  - interrupts
97  - ti,rproc
98  - mboxes
99
100additionalProperties: false
101
102examples:
103  - |
104    /* Example for AM335x SoC */
105    soc {
106        #address-cells = <1>;
107        #size-cells = <1>;
108
109        am335x_mailbox: mailbox {
110            #mbox-cells = <1>;
111        };
112
113        wkup_m3_ipc@1324 {
114           compatible = "ti,am3352-wkup-m3-ipc";
115           reg = <0x1324 0x24>;
116           interrupts = <78>;
117           ti,rproc = <&wkup_m3>;
118           mboxes = <&am335x_mailbox &mbox_wkupm3>;
119           ti,vtt-gpio-pin = <7>;
120        };
121    };
122
123  - |
124    /*
125     * Example for AM473x SoC:
126     * On the AM437x-GP-EVM board, gpio5_7 is wired to enable pin of the DDR VTT
127     * regulator. The 'ddr_vtt_toggle_default' pinmux node configures gpio5_7
128     * for pull-up during normal system operation. However, the DS0 (deep sleep)
129     * state of the pin is configured for pull-down and thus the VTT regulator
130     * will be disabled to save power when IO isolation is active. Note that
131     * this method is an alternative to using the 'ti,vtt-gpio-pin' property.
132     */
133    #include <dt-bindings/pinctrl/am43xx.h>
134    soc {
135        #address-cells = <1>;
136        #size-cells = <1>;
137
138        am437x_mailbox: mailbox {
139            #mbox-cells = <1>;
140        };
141
142        am43xx_pinmux {
143            pinctrl-names = "default";
144            pinctrl-0 = <&ddr3_vtt_toggle_default>;
145
146            ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
147                 pinctrl-single,pins = <
148                    0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7)
149                 >;
150            };
151        };
152
153        wkup_m3_ipc@1324 {
154           compatible = "ti,am4372-wkup-m3-ipc";
155           reg = <0x1324 0x24>;
156           interrupts = <78>;
157           ti,rproc = <&wkup_m3>;
158           mboxes = <&am437x_mailbox &mbox_wkupm3>;
159           ti,set-io-isolation;
160        };
161    };
162
163...
164