1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: |+
8  TI Programmable Real-Time Unit and Industrial Communication Subsystem
9
10maintainers:
11  - Suman Anna <s-anna@ti.com>
12
13description: |+
14
15  The Programmable Real-Time Unit and Industrial Communication Subsystem
16  (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17  Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18  cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19  instruction RAMs, some internal peripheral modules to facilitate industrial
20  communication, and an interrupt controller.
21
22  The programmable nature of the PRUs provide flexibility to implement custom
23  peripheral interfaces, fast real-time responses, or specialized data handling.
24  The common peripheral modules include the following,
25    - an Ethernet MII_RT module with two MII ports
26    - an MDIO port to control external Ethernet PHYs
27    - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
28      Ethernet functions
29    - an Enhanced Capture Module (eCAP)
30    - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31    - a 16550-compatible UART to support PROFIBUS
32    - Enhanced GPIO with async capture and serial support
33
34  A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35  acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36  0x0, but also has access to a secondary Data RAM (primary to the other PRU
37  core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38  by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39  common to both the PRU cores. Each PRU core also has a private instruction
40  RAM, and specific register spaces for Control and Debug functionalities.
41
42  Various sub-modules within a PRU-ICSS subsystem are represented as individual
43  nodes and are defined using a parent-child hierarchy depending on their
44  integration within the IP and the SoC. These nodes are described in the
45  following sections.
46
47
48  PRU-ICSS Node
49  ==============
50  Each PRU-ICSS instance is represented as its own node with the individual PRU
51  processor cores, the memories node, an INTC node and an MDIO node represented
52  as child nodes within this PRUSS node. This node shall be a child of the
53  corresponding interconnect bus nodes or target-module nodes.
54
55  See ../../mfd/syscon.yaml for generic SysCon binding details.
56
57
58properties:
59  $nodename:
60    pattern: "^(pruss|icssg)@[0-9a-f]+$"
61
62  compatible:
63    enum:
64      - ti,am3356-pruss  # for AM335x SoC family
65      - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66      - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67      - ti,am5728-pruss  # for AM57xx SoC family
68      - ti,k2g-pruss     # for 66AK2G SoC family
69      - ti,am654-icssg   # for K3 AM65x SoC family
70      - ti,j721e-icssg   # for K3 J721E SoC family
71
72  reg:
73    maxItems: 1
74
75  "#address-cells":
76    const: 1
77
78  "#size-cells":
79    const: 1
80
81  ranges:
82    maxItems: 1
83
84  dma-ranges:
85    maxItems: 1
86
87  power-domains:
88    description: |
89      This property is as per sci-pm-domain.txt.
90
91patternProperties:
92
93  memories@[a-f0-9]+$:
94    description: |
95      The various Data RAMs within a single PRU-ICSS unit are represented as a
96      single node with the name 'memories'.
97
98    type: object
99
100    properties:
101      reg:
102        minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
103        items:
104          - description: Address and size of the Data RAM0.
105          - description: Address and size of the Data RAM1.
106          - description: |
107              Address and size of the Shared Data RAM. Note that on AM437x one
108              of two PRUSS units don't contain Shared RAM, while the second one
109              has it.
110
111      reg-names:
112        minItems: 2
113        items:
114          - const: dram0
115          - const: dram1
116          - const: shrdram2
117
118    required:
119      - reg
120      - reg-names
121
122    additionalProperties: false
123
124  cfg@[a-f0-9]+$:
125    description: |
126      PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
127
128    type: object
129
130    properties:
131      compatible:
132        items:
133          - const: ti,pruss-cfg
134          - const: syscon
135
136      "#address-cells":
137        const: 1
138
139      "#size-cells":
140        const: 1
141
142      reg:
143        maxItems: 1
144
145      ranges:
146        maxItems: 1
147
148      clocks:
149        type: object
150
151        properties:
152          "#address-cells":
153            const: 1
154
155          "#size-cells":
156            const: 0
157
158        patternProperties:
159          coreclk-mux@[a-f0-9]+$:
160            description: |
161              This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
162              core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
163              ICSSG_ICLK.  This node models this clock mux and should have the
164              name "coreclk-mux".
165
166            type: object
167
168            properties:
169              '#clock-cells':
170                const: 0
171
172              clocks:
173                items:
174                  - description: ICSSG_CORE Clock
175                  - description: ICSSG_ICLK Clock
176
177              assigned-clocks:
178                maxItems: 1
179
180              assigned-clock-parents:
181                maxItems: 1
182                description: |
183                  Standard assigned-clocks-parents definition used for selecting
184                  mux parent (one of the mux input).
185
186              reg:
187                maxItems: 1
188
189            required:
190              - clocks
191
192            additionalProperties: false
193
194          iepclk-mux@[a-f0-9]+$:
195            description: |
196              The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
197              CORE_CLK (OCP_CLK in older SoCs). This node models this clock
198              mux and should have the name "iepclk-mux".
199
200            type: object
201
202            properties:
203              '#clock-cells':
204                const: 0
205
206              clocks:
207                items:
208                  - description: ICSSG_IEP Clock
209                  - description: Core Clock (OCP Clock in older SoCs)
210
211              assigned-clocks:
212                maxItems: 1
213
214              assigned-clock-parents:
215                maxItems: 1
216                description: |
217                  Standard assigned-clocks-parents definition used for selecting
218                  mux parent (one of the mux input).
219
220              reg:
221                maxItems: 1
222
223            required:
224              - clocks
225
226            additionalProperties: false
227
228        additionalProperties: false
229
230  iep@[a-f0-9]+$:
231    description: |
232      Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
233      functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
234      AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
235      is used for creating PTP clocks and generating PPS signals.
236
237    type: object
238
239  mii-rt@[a-f0-9]+$:
240    description: |
241      Real-Time Ethernet to support multiple industrial communication protocols.
242      MII-RT sub-module represented as a SysCon.
243
244    type: object
245
246    properties:
247      compatible:
248        items:
249          - const: ti,pruss-mii
250          - const: syscon
251
252      reg:
253        maxItems: 1
254
255    additionalProperties: false
256
257  mii-g-rt@[a-f0-9]+$:
258    description: |
259      The Real-time Media Independent Interface to support multiple industrial
260      communication protocols (G stands for Gigabit). MII-G-RT sub-module
261      represented as a SysCon.
262
263    type: object
264
265    properties:
266      compatible:
267        items:
268          - const: ti,pruss-mii-g
269          - const: syscon
270
271      reg:
272        maxItems: 1
273
274    additionalProperties: false
275
276  interrupt-controller@[a-f0-9]+$:
277    description: |
278      PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
279      that is common to all the PRU cores. This should be represented as an
280      interrupt-controller node.
281
282    allOf:
283      - $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml#
284
285    type: object
286
287  mdio@[a-f0-9]+$:
288    description: |
289      MDIO Node. Each PRUSS has an MDIO module that can be used to control
290      external PHYs. The MDIO module used within the PRU-ICSS is an instance of
291      the MDIO Controller used in TI Davinci SoCs.
292
293    allOf:
294      - $ref: /schemas/net/ti,davinci-mdio.yaml#
295
296    type: object
297
298  "^(pru|rtu|txpru)@[0-9a-f]+$":
299    description: |
300      PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
301      device through a PRU child node each. Each node can optionally be rendered
302      inactive by using the standard DT string property, "status". The ICSSG IP
303      present on K3 SoCs have additional auxiliary PRU cores with slightly
304      different IP integration.
305
306    allOf:
307      - $ref: /schemas/remoteproc/ti,pru-rproc.yaml#
308
309    type: object
310
311required:
312  - compatible
313  - reg
314  - ranges
315
316additionalProperties: false
317
318# Due to inability of correctly verifying sub-nodes with an @address through
319# the "required" list, the required sub-nodes below are commented out for now.
320
321#required:
322# - memories
323# - interrupt-controller
324# - pru
325
326if:
327  properties:
328    compatible:
329      contains:
330        enum:
331          - ti,k2g-pruss
332          - ti,am654-icssg
333          - ti,j721e-icssg
334then:
335  required:
336    - power-domains
337
338examples:
339  - |
340
341    /* Example 1 AM33xx PRU-ICSS */
342    pruss: pruss@0 {
343        compatible = "ti,am3356-pruss";
344        reg = <0x0 0x80000>;
345        #address-cells = <1>;
346        #size-cells = <1>;
347        ranges;
348
349        pruss_mem: memories@0 {
350            reg = <0x0 0x2000>,
351                  <0x2000 0x2000>,
352                  <0x10000 0x3000>;
353            reg-names = "dram0", "dram1", "shrdram2";
354        };
355
356        pruss_cfg: cfg@26000 {
357            compatible = "ti,pruss-cfg", "syscon";
358            #address-cells = <1>;
359            #size-cells = <1>;
360            reg = <0x26000 0x2000>;
361            ranges = <0x00 0x26000 0x2000>;
362
363            clocks {
364                #address-cells = <1>;
365                #size-cells = <0>;
366
367                pruss_iepclk_mux: iepclk-mux@30 {
368                    reg = <0x30>;
369                    #clock-cells = <0>;
370                    clocks = <&l3_gclk>,        /* icss_iep */
371                             <&pruss_ocp_gclk>; /* icss_ocp */
372                };
373            };
374        };
375
376        pruss_mii_rt: mii-rt@32000 {
377            compatible = "ti,pruss-mii", "syscon";
378            reg = <0x32000 0x58>;
379        };
380
381        pruss_intc: interrupt-controller@20000 {
382            compatible = "ti,pruss-intc";
383            reg = <0x20000 0x2000>;
384            interrupt-controller;
385            #interrupt-cells = <3>;
386            interrupts = <20 21 22 23 24 25 26 27>;
387            interrupt-names = "host_intr0", "host_intr1",
388                              "host_intr2", "host_intr3",
389                              "host_intr4", "host_intr5",
390                              "host_intr6", "host_intr7";
391        };
392
393        pru0: pru@34000 {
394            compatible = "ti,am3356-pru";
395            reg = <0x34000 0x2000>,
396                  <0x22000 0x400>,
397                  <0x22400 0x100>;
398            reg-names = "iram", "control", "debug";
399            firmware-name = "am335x-pru0-fw";
400        };
401
402        pru1: pru@38000 {
403            compatible = "ti,am3356-pru";
404            reg = <0x38000 0x2000>,
405                  <0x24000 0x400>,
406                  <0x24400 0x100>;
407            reg-names = "iram", "control", "debug";
408            firmware-name = "am335x-pru1-fw";
409        };
410
411        pruss_mdio: mdio@32400 {
412            compatible = "ti,davinci_mdio";
413            reg = <0x32400 0x90>;
414            clocks = <&dpll_core_m4_ck>;
415            clock-names = "fck";
416            bus_freq = <1000000>;
417            #address-cells = <1>;
418            #size-cells = <0>;
419        };
420    };
421
422  - |
423
424    /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
425    #include <dt-bindings/interrupt-controller/arm-gic.h>
426    pruss1: pruss@0 {
427        compatible = "ti,am4376-pruss1";
428        reg = <0x0 0x40000>;
429        #address-cells = <1>;
430        #size-cells = <1>;
431        ranges;
432
433        pruss1_mem: memories@0 {
434            reg = <0x0 0x2000>,
435                  <0x2000 0x2000>,
436                  <0x10000 0x8000>;
437            reg-names = "dram0", "dram1", "shrdram2";
438        };
439
440        pruss1_cfg: cfg@26000 {
441            compatible = "ti,pruss-cfg", "syscon";
442            #address-cells = <1>;
443            #size-cells = <1>;
444            reg = <0x26000 0x2000>;
445            ranges = <0x00 0x26000 0x2000>;
446
447            clocks {
448                #address-cells = <1>;
449                #size-cells = <0>;
450
451                pruss1_iepclk_mux: iepclk-mux@30 {
452                    reg = <0x30>;
453                    #clock-cells = <0>;
454                    clocks = <&sysclk_div>,     /* icss_iep */
455                             <&pruss_ocp_gclk>; /* icss_ocp */
456                };
457            };
458        };
459
460        pruss1_mii_rt: mii-rt@32000 {
461            compatible = "ti,pruss-mii", "syscon";
462            reg = <0x32000 0x58>;
463        };
464
465        pruss1_intc: interrupt-controller@20000 {
466            compatible = "ti,pruss-intc";
467            reg = <0x20000 0x2000>;
468            interrupt-controller;
469            #interrupt-cells = <3>;
470            interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
471                         <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
472                         <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
473                         <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
474                         <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
475                         <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
476                         <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
477            interrupt-names = "host_intr0", "host_intr1",
478                              "host_intr2", "host_intr3",
479                              "host_intr4",
480                              "host_intr6", "host_intr7";
481            ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
482        };
483
484        pru1_0: pru@34000 {
485            compatible = "ti,am4376-pru";
486            reg = <0x34000 0x3000>,
487                  <0x22000 0x400>,
488                  <0x22400 0x100>;
489            reg-names = "iram", "control", "debug";
490            firmware-name = "am437x-pru1_0-fw";
491        };
492
493        pru1_1: pru@38000 {
494            compatible = "ti,am4376-pru";
495            reg = <0x38000 0x3000>,
496                  <0x24000 0x400>,
497                  <0x24400 0x100>;
498            reg-names = "iram", "control", "debug";
499            firmware-name = "am437x-pru1_1-fw";
500        };
501
502        pruss1_mdio: mdio@32400 {
503            compatible = "ti,davinci_mdio";
504            reg = <0x32400 0x90>;
505            clocks = <&dpll_core_m4_ck>;
506            clock-names = "fck";
507            bus_freq = <1000000>;
508            #address-cells = <1>;
509            #size-cells = <0>;
510        };
511    };
512
513...
514