1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: |+
8  TI Programmable Real-Time Unit and Industrial Communication Subsystem
9
10maintainers:
11  - Suman Anna <s-anna@ti.com>
12
13description: |+
14
15  The Programmable Real-Time Unit and Industrial Communication Subsystem
16  (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17  Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18  cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
19  instruction RAMs, some internal peripheral modules to facilitate industrial
20  communication, and an interrupt controller.
21
22  The programmable nature of the PRUs provide flexibility to implement custom
23  peripheral interfaces, fast real-time responses, or specialized data handling.
24  The common peripheral modules include the following,
25    - an Ethernet MII_RT module with two MII ports
26    - an MDIO port to control external Ethernet PHYs
27    - an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial
28      Ethernet functions
29    - an Enhanced Capture Module (eCAP)
30    - an Industrial Ethernet Timer with 7/9 capture and 16 compare events
31    - a 16550-compatible UART to support PROFIBUS
32    - Enhanced GPIO with async capture and serial support
33
34  A PRU-ICSS subsystem can have up to three shared data memories. A PRU core
35  acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
36  0x0, but also has access to a secondary Data RAM (primary to the other PRU
37  core) at its address 0x2000. A shared Data RAM, if present, can be accessed
38  by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are
39  common to both the PRU cores. Each PRU core also has a private instruction
40  RAM, and specific register spaces for Control and Debug functionalities.
41
42  Various sub-modules within a PRU-ICSS subsystem are represented as individual
43  nodes and are defined using a parent-child hierarchy depending on their
44  integration within the IP and the SoC. These nodes are described in the
45  following sections.
46
47
48  PRU-ICSS Node
49  ==============
50  Each PRU-ICSS instance is represented as its own node with the individual PRU
51  processor cores, the memories node, an INTC node and an MDIO node represented
52  as child nodes within this PRUSS node. This node shall be a child of the
53  corresponding interconnect bus nodes or target-module nodes.
54
55  See ../../mfd/syscon.yaml for generic SysCon binding details.
56
57
58properties:
59  $nodename:
60    pattern: "^(pruss|icssg)@[0-9a-f]+$"
61
62  compatible:
63    enum:
64      - ti,am3356-pruss  # for AM335x SoC family
65      - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
66      - ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1
67      - ti,am5728-pruss  # for AM57xx SoC family
68      - ti,k2g-pruss     # for 66AK2G SoC family
69      - ti,am654-icssg   # for K3 AM65x SoC family
70      - ti,j721e-icssg   # for K3 J721E SoC family
71
72  reg:
73    maxItems: 1
74
75  "#address-cells":
76    const: 1
77
78  "#size-cells":
79    const: 1
80
81  ranges:
82    maxItems: 1
83
84  power-domains:
85    description: |
86      This property is as per sci-pm-domain.txt.
87
88patternProperties:
89
90  memories@[a-f0-9]+$:
91    description: |
92      The various Data RAMs within a single PRU-ICSS unit are represented as a
93      single node with the name 'memories'.
94
95    type: object
96
97    properties:
98      reg:
99        minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
100        maxItems: 3
101        items:
102          - description: Address and size of the Data RAM0.
103          - description: Address and size of the Data RAM1.
104          - description: |
105              Address and size of the Shared Data RAM. Note that on AM437x one
106              of two PRUSS units don't contain Shared RAM, while the second one
107              has it.
108
109      reg-names:
110        minItems: 2
111        maxItems: 3
112        items:
113          - const: dram0
114          - const: dram1
115          - const: shrdram2
116
117    required:
118      - reg
119      - reg-names
120
121    additionalProperties: false
122
123  cfg@[a-f0-9]+$:
124    description: |
125      PRU-ICSS configuration space. CFG sub-module represented as a SysCon.
126
127    type: object
128
129    properties:
130      compatible:
131        items:
132          - const: ti,pruss-cfg
133          - const: syscon
134
135      "#address-cells":
136        const: 1
137
138      "#size-cells":
139        const: 1
140
141      reg:
142        maxItems: 1
143
144      ranges:
145        maxItems: 1
146
147      clocks:
148        type: object
149
150        properties:
151          "#address-cells":
152            const: 1
153
154          "#size-cells":
155            const: 0
156
157        patternProperties:
158          coreclk-mux@[a-f0-9]+$:
159            description: |
160              This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
161              core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
162              ICSSG_ICLK.  This node models this clock mux and should have the
163              name "coreclk-mux".
164
165            type: object
166
167            properties:
168              '#clock-cells':
169                const: 0
170
171              clocks:
172                items:
173                  - description: ICSSG_CORE Clock
174                  - description: ICSSG_ICLK Clock
175
176              assigned-clocks:
177                maxItems: 1
178
179              assigned-clock-parents:
180                maxItems: 1
181                description: |
182                  Standard assigned-clocks-parents definition used for selecting
183                  mux parent (one of the mux input).
184
185              reg:
186                maxItems: 1
187
188            required:
189              - clocks
190
191            additionalProperties: false
192
193          iepclk-mux@[a-f0-9]+$:
194            description: |
195              The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
196              CORE_CLK (OCP_CLK in older SoCs). This node models this clock
197              mux and should have the name "iepclk-mux".
198
199            type: object
200
201            properties:
202              '#clock-cells':
203                const: 0
204
205              clocks:
206                items:
207                  - description: ICSSG_IEP Clock
208                  - description: Core Clock (OCP Clock in older SoCs)
209
210              assigned-clocks:
211                maxItems: 1
212
213              assigned-clock-parents:
214                maxItems: 1
215                description: |
216                  Standard assigned-clocks-parents definition used for selecting
217                  mux parent (one of the mux input).
218
219              reg:
220                maxItems: 1
221
222            required:
223              - clocks
224
225            additionalProperties: false
226
227        additionalProperties: false
228
229  iep@[a-f0-9]+$:
230    description: |
231      Industrial Ethernet Peripheral to manage/generate Industrial Ethernet
232      functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x,
233      AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP
234      is used for creating PTP clocks and generating PPS signals.
235
236    type: object
237
238  mii-rt@[a-f0-9]+$:
239    description: |
240      Real-Time Ethernet to support multiple industrial communication protocols.
241      MII-RT sub-module represented as a SysCon.
242
243    type: object
244
245    properties:
246      compatible:
247        items:
248          - const: ti,pruss-mii
249          - const: syscon
250
251      reg:
252        maxItems: 1
253
254    additionalProperties: false
255
256  mii-g-rt@[a-f0-9]+$:
257    description: |
258      The Real-time Media Independent Interface to support multiple industrial
259      communication protocols (G stands for Gigabit). MII-G-RT sub-module
260      represented as a SysCon.
261
262    type: object
263
264    properties:
265      compatible:
266        items:
267          - const: ti,pruss-mii-g
268          - const: syscon
269
270      reg:
271        maxItems: 1
272
273    additionalProperties: false
274
275  interrupt-controller@[a-f0-9]+$:
276    description: |
277      PRUSS INTC Node. Each PRUSS has a single interrupt controller instance
278      that is common to all the PRU cores. This should be represented as an
279      interrupt-controller node.
280
281    type: object
282
283  mdio@[a-f0-9]+$:
284    description: |
285      MDIO Node. Each PRUSS has an MDIO module that can be used to control
286      external PHYs. The MDIO module used within the PRU-ICSS is an instance of
287      the MDIO Controller used in TI Davinci SoCs.
288
289    allOf:
290      - $ref: /schemas/net/ti,davinci-mdio.yaml#
291
292    type: object
293
294  "^(pru|rtu|txpru)@[0-9a-f]+$":
295    description: |
296      PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc
297      device through a PRU child node each. Each node can optionally be rendered
298      inactive by using the standard DT string property, "status". The ICSSG IP
299      present on K3 SoCs have additional auxiliary PRU cores with slightly
300      different IP integration.
301
302    type: object
303
304required:
305  - compatible
306  - reg
307  - ranges
308
309additionalProperties: false
310
311# Due to inability of correctly verifying sub-nodes with an @address through
312# the "required" list, the required sub-nodes below are commented out for now.
313
314#required:
315# - memories
316# - interrupt-controller
317# - pru
318
319if:
320  properties:
321    compatible:
322      contains:
323        enum:
324          - ti,k2g-pruss
325          - ti,am654-icssg
326          - ti,j721e-icssg
327then:
328  required:
329    - power-domains
330
331examples:
332  - |
333
334    /* Example 1 AM33xx PRU-ICSS */
335    pruss: pruss@0 {
336        compatible = "ti,am3356-pruss";
337        reg = <0x0 0x80000>;
338        #address-cells = <1>;
339        #size-cells = <1>;
340        ranges;
341
342        pruss_mem: memories@0 {
343            reg = <0x0 0x2000>,
344                  <0x2000 0x2000>,
345                  <0x10000 0x3000>;
346            reg-names = "dram0", "dram1", "shrdram2";
347        };
348
349        pruss_cfg: cfg@26000 {
350            compatible = "ti,pruss-cfg", "syscon";
351            #address-cells = <1>;
352            #size-cells = <1>;
353            reg = <0x26000 0x2000>;
354            ranges = <0x00 0x26000 0x2000>;
355
356            clocks {
357                #address-cells = <1>;
358                #size-cells = <0>;
359
360                pruss_iepclk_mux: iepclk-mux@30 {
361                    reg = <0x30>;
362                    #clock-cells = <0>;
363                    clocks = <&l3_gclk>,        /* icss_iep */
364                             <&pruss_ocp_gclk>; /* icss_ocp */
365                };
366            };
367        };
368
369        pruss_mii_rt: mii-rt@32000 {
370            compatible = "ti,pruss-mii", "syscon";
371            reg = <0x32000 0x58>;
372        };
373
374        pruss_mdio: mdio@32400 {
375            compatible = "ti,davinci_mdio";
376            reg = <0x32400 0x90>;
377            clocks = <&dpll_core_m4_ck>;
378            clock-names = "fck";
379            bus_freq = <1000000>;
380            #address-cells = <1>;
381            #size-cells = <0>;
382        };
383    };
384
385  - |
386
387    /* Example 2 AM43xx PRU-ICSS with PRUSS1 node */
388    #include <dt-bindings/interrupt-controller/arm-gic.h>
389    pruss1: pruss@0 {
390        compatible = "ti,am4376-pruss1";
391        reg = <0x0 0x40000>;
392        #address-cells = <1>;
393        #size-cells = <1>;
394        ranges;
395
396        pruss1_mem: memories@0 {
397            reg = <0x0 0x2000>,
398                  <0x2000 0x2000>,
399                  <0x10000 0x8000>;
400            reg-names = "dram0", "dram1", "shrdram2";
401        };
402
403        pruss1_cfg: cfg@26000 {
404            compatible = "ti,pruss-cfg", "syscon";
405            #address-cells = <1>;
406            #size-cells = <1>;
407            reg = <0x26000 0x2000>;
408            ranges = <0x00 0x26000 0x2000>;
409
410            clocks {
411                #address-cells = <1>;
412                #size-cells = <0>;
413
414                pruss1_iepclk_mux: iepclk-mux@30 {
415                    reg = <0x30>;
416                    #clock-cells = <0>;
417                    clocks = <&sysclk_div>,     /* icss_iep */
418                             <&pruss_ocp_gclk>; /* icss_ocp */
419                };
420            };
421        };
422
423        pruss1_mii_rt: mii-rt@32000 {
424            compatible = "ti,pruss-mii", "syscon";
425            reg = <0x32000 0x58>;
426        };
427
428        pruss1_mdio: mdio@32400 {
429            compatible = "ti,davinci_mdio";
430            reg = <0x32400 0x90>;
431            clocks = <&dpll_core_m4_ck>;
432            clock-names = "fck";
433            bus_freq = <1000000>;
434            #address-cells = <1>;
435            #size-cells = <0>;
436        };
437    };
438
439...
440