1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung's Exynos USI (Universal Serial Interface) binding
8
9maintainers:
10  - Sam Protsenko <semen.protsenko@linaro.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
12
13description: |
14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15  USI shares almost all internal circuits within each protocol, so only one
16  protocol can be chosen at a time. USI is modeled as a node with zero or more
17  child nodes, each representing a serial sub-node device. The mode setting
18  selects which particular function will be used.
19
20  Refer to next bindings documentation for information on protocol subnodes that
21  can exist under USI node:
22
23  [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
24  [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
25  [3] Documentation/devicetree/bindings/spi/spi-samsung.txt
26
27properties:
28  $nodename:
29    pattern: "^usi@[0-9a-f]+$"
30
31  compatible:
32    enum:
33      - samsung,exynos850-usi   # for USIv2 (Exynos850, ExynosAutoV9)
34
35  reg: true
36
37  clocks: true
38
39  clock-names: true
40
41  ranges: true
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  samsung,sysreg:
50    $ref: /schemas/types.yaml#/definitions/phandle-array
51    items:
52      - items:
53          - description: phandle to System Register syscon node
54          - description: offset of SW_CONF register for this USI controller
55    description:
56      Should be phandle/offset pair. The phandle to System Register syscon node
57      (for the same domain where this USI controller resides) and the offset
58      of SW_CONF register for this USI controller.
59
60  samsung,mode:
61    $ref: /schemas/types.yaml#/definitions/uint32
62    description:
63      Selects USI function (which serial protocol to use). Refer to
64      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
65
66  samsung,clkreq-on:
67    type: boolean
68    description:
69      Enable this property if underlying protocol requires the clock to be
70      continuously provided without automatic gating. As suggested by SoC
71      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
72      multi-master mode. Usually this property is needed if USI mode is set
73      to "UART".
74
75      This property is optional.
76
77patternProperties:
78  # All other properties should be child nodes
79  "^(serial|spi|i2c)@[0-9a-f]+$":
80    type: object
81    description: Child node describing underlying USI serial protocol
82
83required:
84  - compatible
85  - ranges
86  - "#address-cells"
87  - "#size-cells"
88  - samsung,sysreg
89  - samsung,mode
90
91if:
92  properties:
93    compatible:
94      contains:
95        enum:
96          - samsung,exynos850-usi
97
98then:
99  properties:
100    reg:
101      maxItems: 1
102
103    clocks:
104      items:
105        - description: Bus (APB) clock
106        - description: Operating clock for UART/SPI/I2C protocol
107
108    clock-names:
109      items:
110        - const: pclk
111        - const: ipclk
112
113  required:
114    - reg
115    - clocks
116    - clock-names
117
118else:
119  properties:
120    reg: false
121    clocks: false
122    clock-names: false
123    samsung,clkreq-on: false
124
125additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/arm-gic.h>
130    #include <dt-bindings/soc/samsung,exynos-usi.h>
131
132    usi0: usi@138200c0 {
133        compatible = "samsung,exynos850-usi";
134        reg = <0x138200c0 0x20>;
135        samsung,sysreg = <&sysreg_peri 0x1010>;
136        samsung,mode = <USI_V2_UART>;
137        samsung,clkreq-on; /* needed for UART mode */
138        #address-cells = <1>;
139        #size-cells = <1>;
140        ranges;
141        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
142        clock-names = "pclk", "ipclk";
143
144        serial_0: serial@13820000 {
145            compatible = "samsung,exynos850-uart";
146            reg = <0x13820000 0xc0>;
147            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
148            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
149            clock-names = "uart", "clk_uart_baud0";
150            status = "disabled";
151        };
152
153        hsi2c_0: i2c@13820000 {
154            compatible = "samsung,exynosautov9-hsi2c";
155            reg = <0x13820000 0xc0>;
156            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
157            #address-cells = <1>;
158            #size-cells = <0>;
159            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
160            clock-names = "hsi2c", "hsi2c_pclk";
161            status = "disabled";
162        };
163    };
164