1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung's Exynos USI (Universal Serial Interface) binding
8
9maintainers:
10  - Sam Protsenko <semen.protsenko@linaro.org>
11  - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
12
13description: |
14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
15  USI shares almost all internal circuits within each protocol, so only one
16  protocol can be chosen at a time. USI is modeled as a node with zero or more
17  child nodes, each representing a serial sub-node device. The mode setting
18  selects which particular function will be used.
19
20  Refer to next bindings documentation for information on protocol subnodes that
21  can exist under USI node:
22
23  [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
24  [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
25  [3] Documentation/devicetree/bindings/spi/spi-samsung.txt
26
27properties:
28  $nodename:
29    pattern: "^usi@[0-9a-f]+$"
30
31  compatible:
32    enum:
33      - samsung,exynos850-usi   # for USIv2 (Exynos850, ExynosAutoV9)
34
35  reg: true
36
37  clocks: true
38
39  clock-names: true
40
41  ranges: true
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  samsung,sysreg:
50    $ref: /schemas/types.yaml#/definitions/phandle-array
51    description:
52      Should be phandle/offset pair. The phandle to System Register syscon node
53      (for the same domain where this USI controller resides) and the offset
54      of SW_CONF register for this USI controller.
55
56  samsung,mode:
57    $ref: /schemas/types.yaml#/definitions/uint32
58    description:
59      Selects USI function (which serial protocol to use). Refer to
60      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
61
62  samsung,clkreq-on:
63    type: boolean
64    description:
65      Enable this property if underlying protocol requires the clock to be
66      continuously provided without automatic gating. As suggested by SoC
67      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
68      multi-master mode. Usually this property is needed if USI mode is set
69      to "UART".
70
71      This property is optional.
72
73patternProperties:
74  # All other properties should be child nodes
75  "^(serial|spi|i2c)@[0-9a-f]+$":
76    type: object
77    description: Child node describing underlying USI serial protocol
78
79required:
80  - compatible
81  - ranges
82  - "#address-cells"
83  - "#size-cells"
84  - samsung,sysreg
85  - samsung,mode
86
87if:
88  properties:
89    compatible:
90      contains:
91        enum:
92          - samsung,exynos850-usi
93
94then:
95  properties:
96    reg:
97      maxItems: 1
98
99    clocks:
100      items:
101        - description: Bus (APB) clock
102        - description: Operating clock for UART/SPI/I2C protocol
103
104    clock-names:
105      items:
106        - const: pclk
107        - const: ipclk
108
109  required:
110    - reg
111    - clocks
112    - clock-names
113
114else:
115  properties:
116    reg: false
117    clocks: false
118    clock-names: false
119    samsung,clkreq-on: false
120
121additionalProperties: false
122
123examples:
124  - |
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126    #include <dt-bindings/soc/samsung,exynos-usi.h>
127
128    usi0: usi@138200c0 {
129        compatible = "samsung,exynos850-usi";
130        reg = <0x138200c0 0x20>;
131        samsung,sysreg = <&sysreg_peri 0x1010>;
132        samsung,mode = <USI_V2_UART>;
133        samsung,clkreq-on; /* needed for UART mode */
134        #address-cells = <1>;
135        #size-cells = <1>;
136        ranges;
137        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
138        clock-names = "pclk", "ipclk";
139
140        serial_0: serial@13820000 {
141            compatible = "samsung,exynos850-uart";
142            reg = <0x13820000 0xc0>;
143            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
144            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
145            clock-names = "uart", "clk_uart_baud0";
146            status = "disabled";
147        };
148
149        hsi2c_0: i2c@13820000 {
150            compatible = "samsung,exynosautov9-hsi2c";
151            reg = <0x13820000 0xc0>;
152            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
153            #address-cells = <1>;
154            #size-cells = <0>;
155            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
156            clock-names = "hsi2c", "hsi2c_pclk";
157            status = "disabled";
158        };
159    };
160