1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm RPMH RSC
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Resource Power Manager Hardened (RPMH) is the mechanism for communicating
14  with the hardened resource accelerators on Qualcomm SoCs. Requests to the
15  resources can be written to the Trigger Command Set (TCS)  registers and
16  using a (addr, val) pair and triggered. Messages in the TCS are then sent in
17  sequence over an internal bus.
18
19  The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
20  (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and
21  active/wake resource requests. Multiple such DRVs can exist in a SoC and can
22  be written to from Linux. The structure of each DRV follows the same template
23  with a few variations that are captured by the properties here.
24
25  A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
26  have powered off to facilitate idle power saving. TCS could be classified as::
27    ACTIVE  - Triggered by Linux
28    SLEEP   - Triggered by F/W
29    WAKE    - Triggered by F/W
30    CONTROL - Triggered by F/W
31  See also:: <dt-bindings/soc/qcom,rpmh-rsc.h>
32
33  The order in which they are described in the DT, should match the hardware
34  configuration.
35
36  Requests can be made for the state of a resource, when the subsystem is
37  active or idle. When all subsystems like Modem, GPU, CPU are idle, the
38  resource state will be an aggregate of the sleep votes from each of those
39  subsystems. Clients may request a sleep value for their shared resources in
40  addition to the active mode requests.
41
42  Drivers that want to use the RSC to communicate with RPMH must specify their
43  bindings as child nodes of the RSC controllers they wish to communicate with.
44
45properties:
46  compatible:
47    const: qcom,rpmh-rsc
48
49  interrupts:
50    minItems: 1
51    maxItems: 4
52    description:
53      The interrupt that trips when a message complete/response is received for
54      this DRV from the accelerators.
55      Number of interrupts must match number of DRV blocks.
56
57  label:
58    description:
59      Name for the RSC. The name would be used in trace logs.
60
61  qcom,drv-id:
62    $ref: /schemas/types.yaml#/definitions/uint32
63    description:
64      The ID of the DRV in the RSC block that will be used by this controller.
65
66  qcom,tcs-config:
67    $ref: /schemas/types.yaml#/definitions/uint32-matrix
68    minItems: 4
69    maxItems: 4
70    items:
71      items:
72        - description: |
73            TCS type::
74             - ACTIVE_TCS
75             - SLEEP_TCS
76             - WAKE_TCS
77             - CONTROL_TCS
78          enum: [ 0, 1, 2, 3 ]
79        - description: Number of TCS
80    description: |
81      The tuple defining the configuration of TCS. Must have two cells which
82      describe each TCS type.  The order of the TCS must match the hardware
83      configuration.
84
85  qcom,tcs-offset:
86    $ref: /schemas/types.yaml#/definitions/uint32
87    description:
88      The offset of the TCS blocks.
89
90  reg:
91    minItems: 1
92    maxItems: 4
93
94  reg-names:
95    minItems: 1
96    items:
97      - const: drv-0
98      - const: drv-1
99      - const: drv-2
100      - const: drv-3
101
102  power-domains:
103    maxItems: 1
104
105  bcm-voter:
106    $ref: /schemas/interconnect/qcom,bcm-voter.yaml#
107
108  clock-controller:
109    $ref: /schemas/clock/qcom,rpmhcc.yaml#
110
111  power-controller:
112    $ref: /schemas/power/qcom,rpmpd.yaml#
113
114patternProperties:
115  '^regulators(-[0-9])?$':
116    $ref: /schemas/regulator/qcom,rpmh-regulator.yaml#
117    unevaluatedProperties: false
118
119required:
120  - compatible
121  - interrupts
122  - qcom,drv-id
123  - qcom,tcs-config
124  - qcom,tcs-offset
125  - reg
126  - reg-names
127
128additionalProperties: false
129
130examples:
131  - |
132    // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
133    // 2, the register offsets for DRV2 start at 0D00, the register
134    // calculations are like this::
135    // DRV0: 0x179C0000
136    // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
137    // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
138    // TCS-OFFSET: 0xD00
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
141
142    rsc@179c0000 {
143        compatible = "qcom,rpmh-rsc";
144        reg = <0x179c0000 0x10000>,
145              <0x179d0000 0x10000>,
146              <0x179e0000 0x10000>;
147        reg-names = "drv-0", "drv-1", "drv-2";
148        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
149                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
150                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
151        label = "apps_rsc";
152        qcom,tcs-offset = <0xd00>;
153        qcom,drv-id = <2>;
154        qcom,tcs-config = <ACTIVE_TCS  2>,
155                          <SLEEP_TCS   3>,
156                          <WAKE_TCS    3>,
157                          <CONTROL_TCS 1>;
158        power-domains = <&CLUSTER_PD>;
159      };
160
161  - |
162    // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the
163    // register offsets for DRV0 start at 01C00, the register calculations are
164    // like this::
165    // DRV0: 0xAF20000
166    // TCS-OFFSET: 0x1C00
167    #include <dt-bindings/interrupt-controller/arm-gic.h>
168    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
169
170    rsc@af20000 {
171        compatible = "qcom,rpmh-rsc";
172        reg = <0xaf20000 0x10000>;
173        reg-names = "drv-0";
174        interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
175        label = "disp_rsc";
176        qcom,tcs-offset = <0x1c00>;
177        qcom,drv-id = <0>;
178        qcom,tcs-config = <ACTIVE_TCS  0>,
179                          <SLEEP_TCS   1>,
180                          <WAKE_TCS    1>,
181                          <CONTROL_TCS 0>;
182    };
183
184  - |
185    #include <dt-bindings/interrupt-controller/arm-gic.h>
186    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
187    #include <dt-bindings/power/qcom-rpmpd.h>
188
189    rsc@18200000 {
190        compatible = "qcom,rpmh-rsc";
191        reg = <0x18200000 0x10000>,
192              <0x18210000 0x10000>,
193              <0x18220000 0x10000>;
194        reg-names = "drv-0", "drv-1", "drv-2";
195        interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
196                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
197                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
198        label = "apps_rsc";
199        qcom,tcs-offset = <0xd00>;
200        qcom,drv-id = <2>;
201        qcom,tcs-config = <ACTIVE_TCS  2>,
202                          <SLEEP_TCS   3>,
203                          <WAKE_TCS    3>,
204                          <CONTROL_TCS 0>;
205        power-domains = <&CLUSTER_PD>;
206
207        clock-controller {
208            compatible = "qcom,sm8350-rpmh-clk";
209            #clock-cells = <1>;
210            clock-names = "xo";
211            clocks = <&xo_board>;
212        };
213
214        power-controller {
215            compatible = "qcom,sm8350-rpmhpd";
216            #power-domain-cells = <1>;
217            operating-points-v2 = <&rpmhpd_opp_table>;
218
219            rpmhpd_opp_table: opp-table {
220                compatible = "operating-points-v2";
221
222                rpmhpd_opp_ret: opp1 {
223                    opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
224                };
225
226                rpmhpd_opp_min_svs: opp2 {
227                    opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
228                };
229
230                rpmhpd_opp_low_svs: opp3 {
231                    opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
232                };
233
234                rpmhpd_opp_svs: opp4 {
235                    opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
236                };
237
238                rpmhpd_opp_svs_l1: opp5 {
239                    opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
240                };
241
242                rpmhpd_opp_nom: opp6 {
243                    opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
244                };
245
246                rpmhpd_opp_nom_l1: opp7 {
247                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
248                };
249
250                rpmhpd_opp_nom_l2: opp8 {
251                    opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
252                };
253
254                rpmhpd_opp_turbo: opp9 {
255                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
256                };
257
258                rpmhpd_opp_turbo_l1: opp10 {
259                    opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
260                };
261            };
262        };
263
264        bcm-voter {
265            compatible = "qcom,bcm-voter";
266        };
267    };
268