1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: GENI Serial Engine QUP Wrapper Controller
8
9maintainers:
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
12
13description: |
14 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
15 is a programmable module for supporting a wide range of serial interfaces
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
17 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
18 Wrapper controller is modeled as a node with zero or more child nodes each
19 representing a serial engine.
20
21properties:
22  compatible:
23    enum:
24      - qcom,geni-se-qup
25
26  reg:
27    description: QUP wrapper common register address and length.
28    maxItems: 1
29
30  clock-names:
31    items:
32      - const: m-ahb
33      - const: s-ahb
34
35  clocks:
36    items:
37      - description: Master AHB Clock
38      - description: Slave AHB Clock
39
40  "#address-cells":
41     const: 2
42
43  "#size-cells":
44     const: 2
45
46  ranges: true
47
48  interconnects:
49    maxItems: 1
50
51  interconnect-names:
52    const: qup-core
53
54required:
55  - compatible
56  - reg
57  - clock-names
58  - clocks
59  - "#address-cells"
60  - "#size-cells"
61  - ranges
62
63patternProperties:
64  "^.*@[0-9a-f]+$":
65    type: object
66    description: Common properties for GENI Serial Engine based I2C, SPI and
67                 UART controller.
68
69    properties:
70      reg:
71        description: GENI Serial Engine register address and length.
72        maxItems: 1
73
74      clock-names:
75        const: se
76
77      clocks:
78        description: Serial engine core clock needed by the device.
79        maxItems: 1
80
81      interconnects:
82         minItems: 2
83         maxItems: 3
84
85      interconnect-names:
86         minItems: 2
87         items:
88           - const: qup-core
89           - const: qup-config
90           - const: qup-memory
91
92    required:
93      - reg
94      - clock-names
95      - clocks
96
97  "spi@[0-9a-f]+$":
98    type: object
99    description: GENI serial engine based SPI controller. SPI in master mode
100                 supports up to 50MHz, up to four chip selects, programmable
101                 data path from 4 bits to 32 bits and numerous protocol
102                 variants.
103    allOf:
104      - $ref: /spi/spi-controller.yaml#
105
106    properties:
107      compatible:
108        enum:
109          - qcom,geni-spi
110
111      interrupts:
112        maxItems: 1
113
114      "#address-cells":
115         const: 1
116
117      "#size-cells":
118         const: 0
119
120    required:
121      - compatible
122      - interrupts
123      - "#address-cells"
124      - "#size-cells"
125
126  "i2c@[0-9a-f]+$":
127    type: object
128    description: GENI serial engine based I2C controller.
129    allOf:
130      - $ref: /schemas/i2c/i2c-controller.yaml#
131
132    properties:
133      compatible:
134        enum:
135          - qcom,geni-i2c
136
137      interrupts:
138        maxItems: 1
139
140      "#address-cells":
141         const: 1
142
143      "#size-cells":
144         const: 0
145
146      clock-frequency:
147        description: Desired I2C bus clock frequency in Hz.
148        default: 100000
149
150    required:
151      - compatible
152      - interrupts
153      - "#address-cells"
154      - "#size-cells"
155
156  "serial@[0-9a-f]+$":
157    type: object
158    description: GENI Serial Engine based UART Controller.
159    allOf:
160      - $ref: /schemas/serial.yaml#
161
162    properties:
163      compatible:
164        enum:
165          - qcom,geni-uart
166          - qcom,geni-debug-uart
167
168      interrupts:
169        minItems: 1
170        maxItems: 2
171        items:
172          - description: UART core irq
173          - description: Wakeup irq (RX GPIO)
174
175    required:
176      - compatible
177      - interrupts
178
179
180examples:
181  - |
182    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
183    #include <dt-bindings/interrupt-controller/arm-gic.h>
184
185    soc {
186        #address-cells = <2>;
187        #size-cells = <2>;
188
189        geniqup@8c0000 {
190            compatible = "qcom,geni-se-qup";
191            reg = <0 0x008c0000 0 0x6000>;
192            clock-names = "m-ahb", "s-ahb";
193            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
194                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
195            #address-cells = <2>;
196            #size-cells = <2>;
197            ranges;
198
199            i2c0: i2c@a94000 {
200                compatible = "qcom,geni-i2c";
201                reg = <0 0xa94000 0 0x4000>;
202                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
203                clock-names = "se";
204                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
205                pinctrl-names = "default", "sleep";
206                pinctrl-0 = <&qup_1_i2c_5_active>;
207                pinctrl-1 = <&qup_1_i2c_5_sleep>;
208                #address-cells = <1>;
209                #size-cells = <0>;
210            };
211
212            uart0: serial@a88000 {
213                compatible = "qcom,geni-uart";
214                reg = <0 0xa88000 0 0x7000>;
215                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
216                clock-names = "se";
217                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
218                pinctrl-names = "default", "sleep";
219                pinctrl-0 = <&qup_1_uart_3_active>;
220                pinctrl-1 = <&qup_1_uart_3_sleep>;
221            };
222        };
223    };
224
225...
226