138d46b0fSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0-only 238d46b0fSKrzysztof Kozlowski%YAML 1.2 338d46b0fSKrzysztof Kozlowski--- 438d46b0fSKrzysztof Kozlowski$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# 538d46b0fSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 638d46b0fSKrzysztof Kozlowski 738d46b0fSKrzysztof Kozlowskititle: Qualcomm RPMH RSC 838d46b0fSKrzysztof Kozlowski 938d46b0fSKrzysztof Kozlowskimaintainers: 1038d46b0fSKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 1138d46b0fSKrzysztof Kozlowski 1238d46b0fSKrzysztof Kozlowskidescription: | 1338d46b0fSKrzysztof Kozlowski Resource Power Manager Hardened (RPMH) is the mechanism for communicating 1438d46b0fSKrzysztof Kozlowski with the hardened resource accelerators on Qualcomm SoCs. Requests to the 1538d46b0fSKrzysztof Kozlowski resources can be written to the Trigger Command Set (TCS) registers and 1638d46b0fSKrzysztof Kozlowski using a (addr, val) pair and triggered. Messages in the TCS are then sent in 1738d46b0fSKrzysztof Kozlowski sequence over an internal bus. 1838d46b0fSKrzysztof Kozlowski 1938d46b0fSKrzysztof Kozlowski The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity 2038d46b0fSKrzysztof Kozlowski (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and 2138d46b0fSKrzysztof Kozlowski active/wake resource requests. Multiple such DRVs can exist in a SoC and can 2238d46b0fSKrzysztof Kozlowski be written to from Linux. The structure of each DRV follows the same template 2338d46b0fSKrzysztof Kozlowski with a few variations that are captured by the properties here. 2438d46b0fSKrzysztof Kozlowski 2538d46b0fSKrzysztof Kozlowski A TCS may be triggered from Linux or triggered by the F/W after all the CPUs 2638d46b0fSKrzysztof Kozlowski have powered off to facilitate idle power saving. TCS could be classified as:: 2738d46b0fSKrzysztof Kozlowski ACTIVE - Triggered by Linux 2838d46b0fSKrzysztof Kozlowski SLEEP - Triggered by F/W 2938d46b0fSKrzysztof Kozlowski WAKE - Triggered by F/W 3038d46b0fSKrzysztof Kozlowski CONTROL - Triggered by F/W 3138d46b0fSKrzysztof Kozlowski See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> 3238d46b0fSKrzysztof Kozlowski 3338d46b0fSKrzysztof Kozlowski The order in which they are described in the DT, should match the hardware 3438d46b0fSKrzysztof Kozlowski configuration. 3538d46b0fSKrzysztof Kozlowski 3638d46b0fSKrzysztof Kozlowski Requests can be made for the state of a resource, when the subsystem is 3738d46b0fSKrzysztof Kozlowski active or idle. When all subsystems like Modem, GPU, CPU are idle, the 3838d46b0fSKrzysztof Kozlowski resource state will be an aggregate of the sleep votes from each of those 3938d46b0fSKrzysztof Kozlowski subsystems. Clients may request a sleep value for their shared resources in 4038d46b0fSKrzysztof Kozlowski addition to the active mode requests. 4138d46b0fSKrzysztof Kozlowski 4238d46b0fSKrzysztof Kozlowski Drivers that want to use the RSC to communicate with RPMH must specify their 4338d46b0fSKrzysztof Kozlowski bindings as child nodes of the RSC controllers they wish to communicate with. 4438d46b0fSKrzysztof Kozlowski 4538d46b0fSKrzysztof Kozlowskiproperties: 4638d46b0fSKrzysztof Kozlowski compatible: 4738d46b0fSKrzysztof Kozlowski const: qcom,rpmh-rsc 4838d46b0fSKrzysztof Kozlowski 4938d46b0fSKrzysztof Kozlowski interrupts: 5038d46b0fSKrzysztof Kozlowski minItems: 1 5138d46b0fSKrzysztof Kozlowski maxItems: 4 5238d46b0fSKrzysztof Kozlowski description: 5338d46b0fSKrzysztof Kozlowski The interrupt that trips when a message complete/response is received for 5438d46b0fSKrzysztof Kozlowski this DRV from the accelerators. 5538d46b0fSKrzysztof Kozlowski Number of interrupts must match number of DRV blocks. 5638d46b0fSKrzysztof Kozlowski 5738d46b0fSKrzysztof Kozlowski label: 5838d46b0fSKrzysztof Kozlowski description: 5938d46b0fSKrzysztof Kozlowski Name for the RSC. The name would be used in trace logs. 6038d46b0fSKrzysztof Kozlowski 6138d46b0fSKrzysztof Kozlowski qcom,drv-id: 6238d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 6338d46b0fSKrzysztof Kozlowski description: 6438d46b0fSKrzysztof Kozlowski The ID of the DRV in the RSC block that will be used by this controller. 6538d46b0fSKrzysztof Kozlowski 6638d46b0fSKrzysztof Kozlowski qcom,tcs-config: 6738d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32-matrix 68*52b23f12SKrzysztof Kozlowski minItems: 4 69*52b23f12SKrzysztof Kozlowski maxItems: 4 7038d46b0fSKrzysztof Kozlowski items: 71*52b23f12SKrzysztof Kozlowski items: 72*52b23f12SKrzysztof Kozlowski - description: | 73*52b23f12SKrzysztof Kozlowski TCS type:: 74*52b23f12SKrzysztof Kozlowski - ACTIVE_TCS 75*52b23f12SKrzysztof Kozlowski - SLEEP_TCS 76*52b23f12SKrzysztof Kozlowski - WAKE_TCS 77*52b23f12SKrzysztof Kozlowski - CONTROL_TCS 7838d46b0fSKrzysztof Kozlowski enum: [ 0, 1, 2, 3 ] 7938d46b0fSKrzysztof Kozlowski - description: Number of TCS 8038d46b0fSKrzysztof Kozlowski description: | 8138d46b0fSKrzysztof Kozlowski The tuple defining the configuration of TCS. Must have two cells which 8238d46b0fSKrzysztof Kozlowski describe each TCS type. The order of the TCS must match the hardware 8338d46b0fSKrzysztof Kozlowski configuration. 8438d46b0fSKrzysztof Kozlowski 8538d46b0fSKrzysztof Kozlowski qcom,tcs-offset: 8638d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 8738d46b0fSKrzysztof Kozlowski description: 8838d46b0fSKrzysztof Kozlowski The offset of the TCS blocks. 8938d46b0fSKrzysztof Kozlowski 9038d46b0fSKrzysztof Kozlowski reg: 9138d46b0fSKrzysztof Kozlowski minItems: 1 9238d46b0fSKrzysztof Kozlowski maxItems: 4 9338d46b0fSKrzysztof Kozlowski 9438d46b0fSKrzysztof Kozlowski reg-names: 9538d46b0fSKrzysztof Kozlowski minItems: 1 9638d46b0fSKrzysztof Kozlowski items: 9738d46b0fSKrzysztof Kozlowski - const: drv-0 9838d46b0fSKrzysztof Kozlowski - const: drv-1 9938d46b0fSKrzysztof Kozlowski - const: drv-2 10038d46b0fSKrzysztof Kozlowski - const: drv-3 10138d46b0fSKrzysztof Kozlowski 10238d46b0fSKrzysztof Kozlowski bcm-voter: 10338d46b0fSKrzysztof Kozlowski $ref: /schemas/interconnect/qcom,bcm-voter.yaml# 10438d46b0fSKrzysztof Kozlowski 10538d46b0fSKrzysztof Kozlowski clock-controller: 10638d46b0fSKrzysztof Kozlowski $ref: /schemas/clock/qcom,rpmhcc.yaml# 10738d46b0fSKrzysztof Kozlowski 10838d46b0fSKrzysztof Kozlowski power-controller: 10938d46b0fSKrzysztof Kozlowski $ref: /schemas/power/qcom,rpmpd.yaml# 11038d46b0fSKrzysztof Kozlowski 11138d46b0fSKrzysztof KozlowskipatternProperties: 11238d46b0fSKrzysztof Kozlowski '-regulators$': 11338d46b0fSKrzysztof Kozlowski $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# 11438d46b0fSKrzysztof Kozlowski 11538d46b0fSKrzysztof Kozlowskirequired: 11638d46b0fSKrzysztof Kozlowski - compatible 11738d46b0fSKrzysztof Kozlowski - interrupts 11838d46b0fSKrzysztof Kozlowski - qcom,drv-id 11938d46b0fSKrzysztof Kozlowski - qcom,tcs-config 12038d46b0fSKrzysztof Kozlowski - qcom,tcs-offset 12138d46b0fSKrzysztof Kozlowski - reg 12238d46b0fSKrzysztof Kozlowski - reg-names 12338d46b0fSKrzysztof Kozlowski 12438d46b0fSKrzysztof KozlowskiadditionalProperties: false 12538d46b0fSKrzysztof Kozlowski 12638d46b0fSKrzysztof Kozlowskiexamples: 12738d46b0fSKrzysztof Kozlowski - | 12838d46b0fSKrzysztof Kozlowski // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of 12938d46b0fSKrzysztof Kozlowski // 2, the register offsets for DRV2 start at 0D00, the register 13038d46b0fSKrzysztof Kozlowski // calculations are like this:: 13138d46b0fSKrzysztof Kozlowski // DRV0: 0x179C0000 13238d46b0fSKrzysztof Kozlowski // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 13338d46b0fSKrzysztof Kozlowski // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 13438d46b0fSKrzysztof Kozlowski // TCS-OFFSET: 0xD00 13538d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 13638d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 13738d46b0fSKrzysztof Kozlowski 13838d46b0fSKrzysztof Kozlowski rsc@179c0000 { 13938d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 14038d46b0fSKrzysztof Kozlowski reg = <0x179c0000 0x10000>, 14138d46b0fSKrzysztof Kozlowski <0x179d0000 0x10000>, 14238d46b0fSKrzysztof Kozlowski <0x179e0000 0x10000>; 14338d46b0fSKrzysztof Kozlowski reg-names = "drv-0", "drv-1", "drv-2"; 14438d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 14538d46b0fSKrzysztof Kozlowski <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 14638d46b0fSKrzysztof Kozlowski <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 14738d46b0fSKrzysztof Kozlowski label = "apps_rsc"; 14838d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0xd00>; 14938d46b0fSKrzysztof Kozlowski qcom,drv-id = <2>; 15038d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 2>, 15138d46b0fSKrzysztof Kozlowski <SLEEP_TCS 3>, 15238d46b0fSKrzysztof Kozlowski <WAKE_TCS 3>, 15338d46b0fSKrzysztof Kozlowski <CONTROL_TCS 1>; 15438d46b0fSKrzysztof Kozlowski }; 15538d46b0fSKrzysztof Kozlowski 15638d46b0fSKrzysztof Kozlowski - | 15738d46b0fSKrzysztof Kozlowski // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the 15838d46b0fSKrzysztof Kozlowski // register offsets for DRV0 start at 01C00, the register calculations are 15938d46b0fSKrzysztof Kozlowski // like this:: 16038d46b0fSKrzysztof Kozlowski // DRV0: 0xAF20000 16138d46b0fSKrzysztof Kozlowski // TCS-OFFSET: 0x1C00 16238d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 16338d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 16438d46b0fSKrzysztof Kozlowski 16538d46b0fSKrzysztof Kozlowski rsc@af20000 { 16638d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 16738d46b0fSKrzysztof Kozlowski reg = <0xaf20000 0x10000>; 16838d46b0fSKrzysztof Kozlowski reg-names = "drv-0"; 16938d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 17038d46b0fSKrzysztof Kozlowski label = "disp_rsc"; 17138d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0x1c00>; 17238d46b0fSKrzysztof Kozlowski qcom,drv-id = <0>; 17338d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 0>, 17438d46b0fSKrzysztof Kozlowski <SLEEP_TCS 1>, 17538d46b0fSKrzysztof Kozlowski <WAKE_TCS 1>, 17638d46b0fSKrzysztof Kozlowski <CONTROL_TCS 0>; 17738d46b0fSKrzysztof Kozlowski }; 17838d46b0fSKrzysztof Kozlowski 17938d46b0fSKrzysztof Kozlowski - | 18038d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 18138d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 18238d46b0fSKrzysztof Kozlowski #include <dt-bindings/power/qcom-rpmpd.h> 18338d46b0fSKrzysztof Kozlowski 18438d46b0fSKrzysztof Kozlowski rsc@18200000 { 18538d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 18638d46b0fSKrzysztof Kozlowski reg = <0x18200000 0x10000>, 18738d46b0fSKrzysztof Kozlowski <0x18210000 0x10000>, 18838d46b0fSKrzysztof Kozlowski <0x18220000 0x10000>; 18938d46b0fSKrzysztof Kozlowski reg-names = "drv-0", "drv-1", "drv-2"; 19038d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 19138d46b0fSKrzysztof Kozlowski <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 19238d46b0fSKrzysztof Kozlowski <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 19338d46b0fSKrzysztof Kozlowski label = "apps_rsc"; 19438d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0xd00>; 19538d46b0fSKrzysztof Kozlowski qcom,drv-id = <2>; 19638d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 2>, 19738d46b0fSKrzysztof Kozlowski <SLEEP_TCS 3>, 19838d46b0fSKrzysztof Kozlowski <WAKE_TCS 3>, 19938d46b0fSKrzysztof Kozlowski <CONTROL_TCS 0>; 20038d46b0fSKrzysztof Kozlowski 20138d46b0fSKrzysztof Kozlowski clock-controller { 20238d46b0fSKrzysztof Kozlowski compatible = "qcom,sm8350-rpmh-clk"; 20338d46b0fSKrzysztof Kozlowski #clock-cells = <1>; 20438d46b0fSKrzysztof Kozlowski clock-names = "xo"; 20538d46b0fSKrzysztof Kozlowski clocks = <&xo_board>; 20638d46b0fSKrzysztof Kozlowski }; 20738d46b0fSKrzysztof Kozlowski 20838d46b0fSKrzysztof Kozlowski power-controller { 20938d46b0fSKrzysztof Kozlowski compatible = "qcom,sm8350-rpmhpd"; 21038d46b0fSKrzysztof Kozlowski #power-domain-cells = <1>; 21138d46b0fSKrzysztof Kozlowski operating-points-v2 = <&rpmhpd_opp_table>; 21238d46b0fSKrzysztof Kozlowski 21338d46b0fSKrzysztof Kozlowski rpmhpd_opp_table: opp-table { 21438d46b0fSKrzysztof Kozlowski compatible = "operating-points-v2"; 21538d46b0fSKrzysztof Kozlowski 21638d46b0fSKrzysztof Kozlowski rpmhpd_opp_ret: opp1 { 21738d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 21838d46b0fSKrzysztof Kozlowski }; 21938d46b0fSKrzysztof Kozlowski 22038d46b0fSKrzysztof Kozlowski rpmhpd_opp_min_svs: opp2 { 22138d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 22238d46b0fSKrzysztof Kozlowski }; 22338d46b0fSKrzysztof Kozlowski 22438d46b0fSKrzysztof Kozlowski rpmhpd_opp_low_svs: opp3 { 22538d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 22638d46b0fSKrzysztof Kozlowski }; 22738d46b0fSKrzysztof Kozlowski 22838d46b0fSKrzysztof Kozlowski rpmhpd_opp_svs: opp4 { 22938d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 23038d46b0fSKrzysztof Kozlowski }; 23138d46b0fSKrzysztof Kozlowski 23238d46b0fSKrzysztof Kozlowski rpmhpd_opp_svs_l1: opp5 { 23338d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 23438d46b0fSKrzysztof Kozlowski }; 23538d46b0fSKrzysztof Kozlowski 23638d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom: opp6 { 23738d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 23838d46b0fSKrzysztof Kozlowski }; 23938d46b0fSKrzysztof Kozlowski 24038d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom_l1: opp7 { 24138d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 24238d46b0fSKrzysztof Kozlowski }; 24338d46b0fSKrzysztof Kozlowski 24438d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom_l2: opp8 { 24538d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 24638d46b0fSKrzysztof Kozlowski }; 24738d46b0fSKrzysztof Kozlowski 24838d46b0fSKrzysztof Kozlowski rpmhpd_opp_turbo: opp9 { 24938d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 25038d46b0fSKrzysztof Kozlowski }; 25138d46b0fSKrzysztof Kozlowski 25238d46b0fSKrzysztof Kozlowski rpmhpd_opp_turbo_l1: opp10 { 25338d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 25438d46b0fSKrzysztof Kozlowski }; 25538d46b0fSKrzysztof Kozlowski }; 25638d46b0fSKrzysztof Kozlowski }; 25738d46b0fSKrzysztof Kozlowski 25838d46b0fSKrzysztof Kozlowski bcm-voter { 25938d46b0fSKrzysztof Kozlowski compatible = "qcom,bcm-voter"; 26038d46b0fSKrzysztof Kozlowski }; 26138d46b0fSKrzysztof Kozlowski }; 262