1*38d46b0fSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0-only 2*38d46b0fSKrzysztof Kozlowski%YAML 1.2 3*38d46b0fSKrzysztof Kozlowski--- 4*38d46b0fSKrzysztof Kozlowski$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# 5*38d46b0fSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 6*38d46b0fSKrzysztof Kozlowski 7*38d46b0fSKrzysztof Kozlowskititle: Qualcomm RPMH RSC 8*38d46b0fSKrzysztof Kozlowski 9*38d46b0fSKrzysztof Kozlowskimaintainers: 10*38d46b0fSKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 11*38d46b0fSKrzysztof Kozlowski 12*38d46b0fSKrzysztof Kozlowskidescription: | 13*38d46b0fSKrzysztof Kozlowski Resource Power Manager Hardened (RPMH) is the mechanism for communicating 14*38d46b0fSKrzysztof Kozlowski with the hardened resource accelerators on Qualcomm SoCs. Requests to the 15*38d46b0fSKrzysztof Kozlowski resources can be written to the Trigger Command Set (TCS) registers and 16*38d46b0fSKrzysztof Kozlowski using a (addr, val) pair and triggered. Messages in the TCS are then sent in 17*38d46b0fSKrzysztof Kozlowski sequence over an internal bus. 18*38d46b0fSKrzysztof Kozlowski 19*38d46b0fSKrzysztof Kozlowski The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity 20*38d46b0fSKrzysztof Kozlowski (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and 21*38d46b0fSKrzysztof Kozlowski active/wake resource requests. Multiple such DRVs can exist in a SoC and can 22*38d46b0fSKrzysztof Kozlowski be written to from Linux. The structure of each DRV follows the same template 23*38d46b0fSKrzysztof Kozlowski with a few variations that are captured by the properties here. 24*38d46b0fSKrzysztof Kozlowski 25*38d46b0fSKrzysztof Kozlowski A TCS may be triggered from Linux or triggered by the F/W after all the CPUs 26*38d46b0fSKrzysztof Kozlowski have powered off to facilitate idle power saving. TCS could be classified as:: 27*38d46b0fSKrzysztof Kozlowski ACTIVE - Triggered by Linux 28*38d46b0fSKrzysztof Kozlowski SLEEP - Triggered by F/W 29*38d46b0fSKrzysztof Kozlowski WAKE - Triggered by F/W 30*38d46b0fSKrzysztof Kozlowski CONTROL - Triggered by F/W 31*38d46b0fSKrzysztof Kozlowski See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> 32*38d46b0fSKrzysztof Kozlowski 33*38d46b0fSKrzysztof Kozlowski The order in which they are described in the DT, should match the hardware 34*38d46b0fSKrzysztof Kozlowski configuration. 35*38d46b0fSKrzysztof Kozlowski 36*38d46b0fSKrzysztof Kozlowski Requests can be made for the state of a resource, when the subsystem is 37*38d46b0fSKrzysztof Kozlowski active or idle. When all subsystems like Modem, GPU, CPU are idle, the 38*38d46b0fSKrzysztof Kozlowski resource state will be an aggregate of the sleep votes from each of those 39*38d46b0fSKrzysztof Kozlowski subsystems. Clients may request a sleep value for their shared resources in 40*38d46b0fSKrzysztof Kozlowski addition to the active mode requests. 41*38d46b0fSKrzysztof Kozlowski 42*38d46b0fSKrzysztof Kozlowski Drivers that want to use the RSC to communicate with RPMH must specify their 43*38d46b0fSKrzysztof Kozlowski bindings as child nodes of the RSC controllers they wish to communicate with. 44*38d46b0fSKrzysztof Kozlowski 45*38d46b0fSKrzysztof Kozlowskiproperties: 46*38d46b0fSKrzysztof Kozlowski compatible: 47*38d46b0fSKrzysztof Kozlowski const: qcom,rpmh-rsc 48*38d46b0fSKrzysztof Kozlowski 49*38d46b0fSKrzysztof Kozlowski interrupts: 50*38d46b0fSKrzysztof Kozlowski minItems: 1 51*38d46b0fSKrzysztof Kozlowski maxItems: 4 52*38d46b0fSKrzysztof Kozlowski description: 53*38d46b0fSKrzysztof Kozlowski The interrupt that trips when a message complete/response is received for 54*38d46b0fSKrzysztof Kozlowski this DRV from the accelerators. 55*38d46b0fSKrzysztof Kozlowski Number of interrupts must match number of DRV blocks. 56*38d46b0fSKrzysztof Kozlowski 57*38d46b0fSKrzysztof Kozlowski label: 58*38d46b0fSKrzysztof Kozlowski description: 59*38d46b0fSKrzysztof Kozlowski Name for the RSC. The name would be used in trace logs. 60*38d46b0fSKrzysztof Kozlowski 61*38d46b0fSKrzysztof Kozlowski qcom,drv-id: 62*38d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 63*38d46b0fSKrzysztof Kozlowski description: 64*38d46b0fSKrzysztof Kozlowski The ID of the DRV in the RSC block that will be used by this controller. 65*38d46b0fSKrzysztof Kozlowski 66*38d46b0fSKrzysztof Kozlowski qcom,tcs-config: 67*38d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32-matrix 68*38d46b0fSKrzysztof Kozlowski items: 69*38d46b0fSKrzysztof Kozlowski - items: 70*38d46b0fSKrzysztof Kozlowski - description: TCS type 71*38d46b0fSKrzysztof Kozlowski enum: [ 0, 1, 2, 3 ] 72*38d46b0fSKrzysztof Kozlowski - description: Number of TCS 73*38d46b0fSKrzysztof Kozlowski - items: 74*38d46b0fSKrzysztof Kozlowski - description: TCS type 75*38d46b0fSKrzysztof Kozlowski enum: [ 0, 1, 2, 3 ] 76*38d46b0fSKrzysztof Kozlowski - description: Number of TCS 77*38d46b0fSKrzysztof Kozlowski - items: 78*38d46b0fSKrzysztof Kozlowski - description: TCS type 79*38d46b0fSKrzysztof Kozlowski enum: [ 0, 1, 2, 3] 80*38d46b0fSKrzysztof Kozlowski - description: Numbe r of TCS 81*38d46b0fSKrzysztof Kozlowski - items: 82*38d46b0fSKrzysztof Kozlowski - description: TCS type 83*38d46b0fSKrzysztof Kozlowski enum: [ 0, 1, 2, 3 ] 84*38d46b0fSKrzysztof Kozlowski - description: Number of TCS 85*38d46b0fSKrzysztof Kozlowski description: | 86*38d46b0fSKrzysztof Kozlowski The tuple defining the configuration of TCS. Must have two cells which 87*38d46b0fSKrzysztof Kozlowski describe each TCS type. The order of the TCS must match the hardware 88*38d46b0fSKrzysztof Kozlowski configuration. 89*38d46b0fSKrzysztof Kozlowski Cell 1 (TCS Type):: TCS types to be specified:: 90*38d46b0fSKrzysztof Kozlowski - ACTIVE_TCS 91*38d46b0fSKrzysztof Kozlowski - SLEEP_TCS 92*38d46b0fSKrzysztof Kozlowski - WAKE_TCS 93*38d46b0fSKrzysztof Kozlowski - CONTROL_TCS 94*38d46b0fSKrzysztof Kozlowski Cell 2 (Number of TCS):: <u32> 95*38d46b0fSKrzysztof Kozlowski 96*38d46b0fSKrzysztof Kozlowski qcom,tcs-offset: 97*38d46b0fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 98*38d46b0fSKrzysztof Kozlowski description: 99*38d46b0fSKrzysztof Kozlowski The offset of the TCS blocks. 100*38d46b0fSKrzysztof Kozlowski 101*38d46b0fSKrzysztof Kozlowski reg: 102*38d46b0fSKrzysztof Kozlowski minItems: 1 103*38d46b0fSKrzysztof Kozlowski maxItems: 4 104*38d46b0fSKrzysztof Kozlowski 105*38d46b0fSKrzysztof Kozlowski reg-names: 106*38d46b0fSKrzysztof Kozlowski minItems: 1 107*38d46b0fSKrzysztof Kozlowski items: 108*38d46b0fSKrzysztof Kozlowski - const: drv-0 109*38d46b0fSKrzysztof Kozlowski - const: drv-1 110*38d46b0fSKrzysztof Kozlowski - const: drv-2 111*38d46b0fSKrzysztof Kozlowski - const: drv-3 112*38d46b0fSKrzysztof Kozlowski 113*38d46b0fSKrzysztof Kozlowski bcm-voter: 114*38d46b0fSKrzysztof Kozlowski $ref: /schemas/interconnect/qcom,bcm-voter.yaml# 115*38d46b0fSKrzysztof Kozlowski 116*38d46b0fSKrzysztof Kozlowski clock-controller: 117*38d46b0fSKrzysztof Kozlowski $ref: /schemas/clock/qcom,rpmhcc.yaml# 118*38d46b0fSKrzysztof Kozlowski 119*38d46b0fSKrzysztof Kozlowski power-controller: 120*38d46b0fSKrzysztof Kozlowski $ref: /schemas/power/qcom,rpmpd.yaml# 121*38d46b0fSKrzysztof Kozlowski 122*38d46b0fSKrzysztof KozlowskipatternProperties: 123*38d46b0fSKrzysztof Kozlowski '-regulators$': 124*38d46b0fSKrzysztof Kozlowski $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# 125*38d46b0fSKrzysztof Kozlowski 126*38d46b0fSKrzysztof Kozlowskirequired: 127*38d46b0fSKrzysztof Kozlowski - compatible 128*38d46b0fSKrzysztof Kozlowski - interrupts 129*38d46b0fSKrzysztof Kozlowski - qcom,drv-id 130*38d46b0fSKrzysztof Kozlowski - qcom,tcs-config 131*38d46b0fSKrzysztof Kozlowski - qcom,tcs-offset 132*38d46b0fSKrzysztof Kozlowski - reg 133*38d46b0fSKrzysztof Kozlowski - reg-names 134*38d46b0fSKrzysztof Kozlowski 135*38d46b0fSKrzysztof KozlowskiadditionalProperties: false 136*38d46b0fSKrzysztof Kozlowski 137*38d46b0fSKrzysztof Kozlowskiexamples: 138*38d46b0fSKrzysztof Kozlowski - | 139*38d46b0fSKrzysztof Kozlowski // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of 140*38d46b0fSKrzysztof Kozlowski // 2, the register offsets for DRV2 start at 0D00, the register 141*38d46b0fSKrzysztof Kozlowski // calculations are like this:: 142*38d46b0fSKrzysztof Kozlowski // DRV0: 0x179C0000 143*38d46b0fSKrzysztof Kozlowski // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 144*38d46b0fSKrzysztof Kozlowski // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 145*38d46b0fSKrzysztof Kozlowski // TCS-OFFSET: 0xD00 146*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 147*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 148*38d46b0fSKrzysztof Kozlowski 149*38d46b0fSKrzysztof Kozlowski rsc@179c0000 { 150*38d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 151*38d46b0fSKrzysztof Kozlowski reg = <0x179c0000 0x10000>, 152*38d46b0fSKrzysztof Kozlowski <0x179d0000 0x10000>, 153*38d46b0fSKrzysztof Kozlowski <0x179e0000 0x10000>; 154*38d46b0fSKrzysztof Kozlowski reg-names = "drv-0", "drv-1", "drv-2"; 155*38d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 156*38d46b0fSKrzysztof Kozlowski <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 157*38d46b0fSKrzysztof Kozlowski <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 158*38d46b0fSKrzysztof Kozlowski label = "apps_rsc"; 159*38d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0xd00>; 160*38d46b0fSKrzysztof Kozlowski qcom,drv-id = <2>; 161*38d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 2>, 162*38d46b0fSKrzysztof Kozlowski <SLEEP_TCS 3>, 163*38d46b0fSKrzysztof Kozlowski <WAKE_TCS 3>, 164*38d46b0fSKrzysztof Kozlowski <CONTROL_TCS 1>; 165*38d46b0fSKrzysztof Kozlowski }; 166*38d46b0fSKrzysztof Kozlowski 167*38d46b0fSKrzysztof Kozlowski - | 168*38d46b0fSKrzysztof Kozlowski // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the 169*38d46b0fSKrzysztof Kozlowski // register offsets for DRV0 start at 01C00, the register calculations are 170*38d46b0fSKrzysztof Kozlowski // like this:: 171*38d46b0fSKrzysztof Kozlowski // DRV0: 0xAF20000 172*38d46b0fSKrzysztof Kozlowski // TCS-OFFSET: 0x1C00 173*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 174*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 175*38d46b0fSKrzysztof Kozlowski 176*38d46b0fSKrzysztof Kozlowski rsc@af20000 { 177*38d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 178*38d46b0fSKrzysztof Kozlowski reg = <0xaf20000 0x10000>; 179*38d46b0fSKrzysztof Kozlowski reg-names = "drv-0"; 180*38d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 181*38d46b0fSKrzysztof Kozlowski label = "disp_rsc"; 182*38d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0x1c00>; 183*38d46b0fSKrzysztof Kozlowski qcom,drv-id = <0>; 184*38d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 0>, 185*38d46b0fSKrzysztof Kozlowski <SLEEP_TCS 1>, 186*38d46b0fSKrzysztof Kozlowski <WAKE_TCS 1>, 187*38d46b0fSKrzysztof Kozlowski <CONTROL_TCS 0>; 188*38d46b0fSKrzysztof Kozlowski }; 189*38d46b0fSKrzysztof Kozlowski 190*38d46b0fSKrzysztof Kozlowski - | 191*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 192*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,rpmh-rsc.h> 193*38d46b0fSKrzysztof Kozlowski #include <dt-bindings/power/qcom-rpmpd.h> 194*38d46b0fSKrzysztof Kozlowski 195*38d46b0fSKrzysztof Kozlowski rsc@18200000 { 196*38d46b0fSKrzysztof Kozlowski compatible = "qcom,rpmh-rsc"; 197*38d46b0fSKrzysztof Kozlowski reg = <0x18200000 0x10000>, 198*38d46b0fSKrzysztof Kozlowski <0x18210000 0x10000>, 199*38d46b0fSKrzysztof Kozlowski <0x18220000 0x10000>; 200*38d46b0fSKrzysztof Kozlowski reg-names = "drv-0", "drv-1", "drv-2"; 201*38d46b0fSKrzysztof Kozlowski interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 202*38d46b0fSKrzysztof Kozlowski <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 203*38d46b0fSKrzysztof Kozlowski <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 204*38d46b0fSKrzysztof Kozlowski label = "apps_rsc"; 205*38d46b0fSKrzysztof Kozlowski qcom,tcs-offset = <0xd00>; 206*38d46b0fSKrzysztof Kozlowski qcom,drv-id = <2>; 207*38d46b0fSKrzysztof Kozlowski qcom,tcs-config = <ACTIVE_TCS 2>, 208*38d46b0fSKrzysztof Kozlowski <SLEEP_TCS 3>, 209*38d46b0fSKrzysztof Kozlowski <WAKE_TCS 3>, 210*38d46b0fSKrzysztof Kozlowski <CONTROL_TCS 0>; 211*38d46b0fSKrzysztof Kozlowski 212*38d46b0fSKrzysztof Kozlowski clock-controller { 213*38d46b0fSKrzysztof Kozlowski compatible = "qcom,sm8350-rpmh-clk"; 214*38d46b0fSKrzysztof Kozlowski #clock-cells = <1>; 215*38d46b0fSKrzysztof Kozlowski clock-names = "xo"; 216*38d46b0fSKrzysztof Kozlowski clocks = <&xo_board>; 217*38d46b0fSKrzysztof Kozlowski }; 218*38d46b0fSKrzysztof Kozlowski 219*38d46b0fSKrzysztof Kozlowski power-controller { 220*38d46b0fSKrzysztof Kozlowski compatible = "qcom,sm8350-rpmhpd"; 221*38d46b0fSKrzysztof Kozlowski #power-domain-cells = <1>; 222*38d46b0fSKrzysztof Kozlowski operating-points-v2 = <&rpmhpd_opp_table>; 223*38d46b0fSKrzysztof Kozlowski 224*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_table: opp-table { 225*38d46b0fSKrzysztof Kozlowski compatible = "operating-points-v2"; 226*38d46b0fSKrzysztof Kozlowski 227*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_ret: opp1 { 228*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 229*38d46b0fSKrzysztof Kozlowski }; 230*38d46b0fSKrzysztof Kozlowski 231*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_min_svs: opp2 { 232*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 233*38d46b0fSKrzysztof Kozlowski }; 234*38d46b0fSKrzysztof Kozlowski 235*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_low_svs: opp3 { 236*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 237*38d46b0fSKrzysztof Kozlowski }; 238*38d46b0fSKrzysztof Kozlowski 239*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_svs: opp4 { 240*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 241*38d46b0fSKrzysztof Kozlowski }; 242*38d46b0fSKrzysztof Kozlowski 243*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_svs_l1: opp5 { 244*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 245*38d46b0fSKrzysztof Kozlowski }; 246*38d46b0fSKrzysztof Kozlowski 247*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom: opp6 { 248*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 249*38d46b0fSKrzysztof Kozlowski }; 250*38d46b0fSKrzysztof Kozlowski 251*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom_l1: opp7 { 252*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 253*38d46b0fSKrzysztof Kozlowski }; 254*38d46b0fSKrzysztof Kozlowski 255*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_nom_l2: opp8 { 256*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 257*38d46b0fSKrzysztof Kozlowski }; 258*38d46b0fSKrzysztof Kozlowski 259*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_turbo: opp9 { 260*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 261*38d46b0fSKrzysztof Kozlowski }; 262*38d46b0fSKrzysztof Kozlowski 263*38d46b0fSKrzysztof Kozlowski rpmhpd_opp_turbo_l1: opp10 { 264*38d46b0fSKrzysztof Kozlowski opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 265*38d46b0fSKrzysztof Kozlowski }; 266*38d46b0fSKrzysztof Kozlowski }; 267*38d46b0fSKrzysztof Kozlowski }; 268*38d46b0fSKrzysztof Kozlowski 269*38d46b0fSKrzysztof Kozlowski bcm-voter { 270*38d46b0fSKrzysztof Kozlowski compatible = "qcom,bcm-voter"; 271*38d46b0fSKrzysztof Kozlowski }; 272*38d46b0fSKrzysztof Kozlowski }; 273