1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Always-On Subsystem side channel binding 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 12description: 13 This binding describes the hardware component responsible for side channel 14 requests to the always-on subsystem (AOSS), used for certain power management 15 requests that is not handled by the standard RPMh interface. Each client in the 16 SoC has its own block of message RAM and IRQ for communication with the AOSS. 17 The protocol used to communicate in the message RAM is known as Qualcomm 18 Messaging Protocol (QMP) 19 20 The AOSS side channel exposes control over a set of resources, used to control 21 a set of debug related clocks and to affect the low power state of resources 22 related to the secondary subsystems. 23 24properties: 25 compatible: 26 items: 27 - enum: 28 - qcom,sc7180-aoss-qmp 29 - qcom,sc7280-aoss-qmp 30 - qcom,sc8180x-aoss-qmp 31 - qcom,sc8280xp-aoss-qmp 32 - qcom,sdm845-aoss-qmp 33 - qcom,sm6350-aoss-qmp 34 - qcom,sm8150-aoss-qmp 35 - qcom,sm8250-aoss-qmp 36 - qcom,sm8350-aoss-qmp 37 - qcom,sm8450-aoss-qmp 38 - const: qcom,aoss-qmp 39 40 reg: 41 maxItems: 1 42 description: 43 The base address and size of the message RAM for this client's 44 communication with the AOSS 45 46 interrupts: 47 maxItems: 1 48 description: 49 Should specify the AOSS message IRQ for this client 50 51 mboxes: 52 maxItems: 1 53 description: 54 Reference to the mailbox representing the outgoing doorbell in APCS for 55 this client, as described in mailbox/mailbox.txt 56 57 "#clock-cells": 58 const: 0 59 description: 60 The single clock represents the QDSS clock. 61 62required: 63 - compatible 64 - reg 65 - interrupts 66 - mboxes 67 - "#clock-cells" 68 69additionalProperties: false 70 71patternProperties: 72 "^(cx|mx|ebi)$": 73 type: object 74 description: 75 The AOSS side channel also provides the controls for three cooling devices, 76 these are expressed as subnodes of the QMP node. The name of the node is 77 used to identify the resource and must therefor be "cx", "mx" or "ebi". 78 79 properties: 80 "#cooling-cells": 81 const: 2 82 83 required: 84 - "#cooling-cells" 85 86 additionalProperties: false 87 88examples: 89 - | 90 #include <dt-bindings/interrupt-controller/arm-gic.h> 91 92 aoss_qmp: qmp@c300000 { 93 compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; 94 reg = <0x0c300000 0x100000>; 95 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 96 mboxes = <&apss_shared 0>; 97 98 #clock-cells = <0>; 99 100 cx_cdev: cx { 101 #cooling-cells = <2>; 102 }; 103 104 mx_cdev: mx { 105 #cooling-cells = <2>; 106 }; 107 }; 108... 109