1d969f217SRoger Lu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2d969f217SRoger Lu%YAML 1.2
3d969f217SRoger Lu---
4d969f217SRoger Lu$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5d969f217SRoger Lu$schema: http://devicetree.org/meta-schemas/core.yaml#
6d969f217SRoger Lu
7*a612130cSKrzysztof Kozlowskititle: MediaTek Smart Voltage Scaling (SVS)
8d969f217SRoger Lu
9d969f217SRoger Lumaintainers:
10d969f217SRoger Lu  - Roger Lu <roger.lu@mediatek.com>
11d969f217SRoger Lu  - Matthias Brugger <matthias.bgg@gmail.com>
12d969f217SRoger Lu  - Kevin Hilman <khilman@kernel.org>
13d969f217SRoger Lu
14d969f217SRoger Ludescription: |+
15d969f217SRoger Lu  The SVS engine is a piece of hardware which has several
16d969f217SRoger Lu  controllers(banks) for calculating suitable voltage to
17d969f217SRoger Lu  different power domains(CPU/GPU/CCI) according to
18d969f217SRoger Lu  chip process corner, temperatures and other factors. Then DVFS
19d969f217SRoger Lu  driver could apply SVS bank voltage to PMIC/Buck.
20d969f217SRoger Lu
21d969f217SRoger Luproperties:
22d969f217SRoger Lu  compatible:
23d969f217SRoger Lu    enum:
24d969f217SRoger Lu      - mediatek,mt8183-svs
255ed6605fSRoger Lu      - mediatek,mt8192-svs
26d969f217SRoger Lu
27d969f217SRoger Lu  reg:
28d969f217SRoger Lu    maxItems: 1
29d969f217SRoger Lu    description: Address range of the MTK SVS controller.
30d969f217SRoger Lu
31d969f217SRoger Lu  interrupts:
32d969f217SRoger Lu    maxItems: 1
33d969f217SRoger Lu
34d969f217SRoger Lu  clocks:
35d969f217SRoger Lu    maxItems: 1
36d969f217SRoger Lu    description: Main clock for MTK SVS controller to work.
37d969f217SRoger Lu
38d969f217SRoger Lu  clock-names:
39d969f217SRoger Lu    const: main
40d969f217SRoger Lu
41d969f217SRoger Lu  nvmem-cells:
42d969f217SRoger Lu    minItems: 1
43d969f217SRoger Lu    description:
44d969f217SRoger Lu      Phandle to the calibration data provided by a nvmem device.
45d969f217SRoger Lu    items:
46d969f217SRoger Lu      - description: SVS efuse for SVS controller
47d969f217SRoger Lu      - description: Thermal efuse for SVS controller
48d969f217SRoger Lu
49d969f217SRoger Lu  nvmem-cell-names:
50d969f217SRoger Lu    items:
51d969f217SRoger Lu      - const: svs-calibration-data
52d969f217SRoger Lu      - const: t-calibration-data
53d969f217SRoger Lu
545ed6605fSRoger Lu  resets:
555ed6605fSRoger Lu    maxItems: 1
565ed6605fSRoger Lu
575ed6605fSRoger Lu  reset-names:
585ed6605fSRoger Lu    items:
595ed6605fSRoger Lu      - const: svs_rst
605ed6605fSRoger Lu
61d969f217SRoger Lurequired:
62d969f217SRoger Lu  - compatible
63d969f217SRoger Lu  - reg
64d969f217SRoger Lu  - interrupts
65d969f217SRoger Lu  - clocks
66d969f217SRoger Lu  - clock-names
67d969f217SRoger Lu  - nvmem-cells
68d969f217SRoger Lu  - nvmem-cell-names
69d969f217SRoger Lu
70d969f217SRoger LuadditionalProperties: false
71d969f217SRoger Lu
72d969f217SRoger Luexamples:
73d969f217SRoger Lu  - |
74d969f217SRoger Lu    #include <dt-bindings/clock/mt8183-clk.h>
75d969f217SRoger Lu    #include <dt-bindings/interrupt-controller/arm-gic.h>
76d969f217SRoger Lu    #include <dt-bindings/interrupt-controller/irq.h>
77d969f217SRoger Lu
78d969f217SRoger Lu    soc {
79d969f217SRoger Lu        #address-cells = <2>;
80d969f217SRoger Lu        #size-cells = <2>;
81d969f217SRoger Lu
82d969f217SRoger Lu        svs@1100b000 {
83d969f217SRoger Lu            compatible = "mediatek,mt8183-svs";
84d969f217SRoger Lu            reg = <0 0x1100b000 0 0x1000>;
85d969f217SRoger Lu            interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
86d969f217SRoger Lu            clocks = <&infracfg CLK_INFRA_THERM>;
87d969f217SRoger Lu            clock-names = "main";
88d969f217SRoger Lu            nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
89d969f217SRoger Lu            nvmem-cell-names = "svs-calibration-data", "t-calibration-data";
90d969f217SRoger Lu        };
91d969f217SRoger Lu    };
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