1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek mutex
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16  data path or MDP data path.
17  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18  the shadow register.
19  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20  For a description of the MMSYS_CONFIG binding, see
21  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22  for details.
23
24properties:
25  compatible:
26    enum:
27      - mediatek,mt2701-disp-mutex
28      - mediatek,mt2712-disp-mutex
29      - mediatek,mt6795-disp-mutex
30      - mediatek,mt8167-disp-mutex
31      - mediatek,mt8173-disp-mutex
32      - mediatek,mt8183-disp-mutex
33      - mediatek,mt8186-disp-mutex
34      - mediatek,mt8186-mdp3-mutex
35      - mediatek,mt8192-disp-mutex
36      - mediatek,mt8195-disp-mutex
37
38  reg:
39    maxItems: 1
40
41  interrupts:
42    maxItems: 1
43
44  power-domains:
45    description: A phandle and PM domain specifier as defined by bindings of
46      the power controller specified by phandle. See
47      Documentation/devicetree/bindings/power/power-domain.yaml for details.
48
49  clocks:
50    items:
51      - description: MUTEX Clock
52
53  mediatek,gce-events:
54    description:
55      The event id which is mapping to the specific hardware event signal
56      to gce. The event id is defined in the gce header
57      include/dt-bindings/gce/<chip>-gce.h of each chips.
58    $ref: /schemas/types.yaml#/definitions/uint32-array
59
60  mediatek,gce-client-reg:
61    $ref: /schemas/types.yaml#/definitions/phandle-array
62    items:
63      items:
64        - description: phandle of GCE
65        - description: GCE subsys id
66        - description: register offset
67        - description: register size
68    description: The register of client driver can be configured by gce with
69      4 arguments defined in this property. Each GCE subsys id is mapping to
70      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
71
72required:
73  - compatible
74  - reg
75  - interrupts
76  - power-domains
77  - clocks
78
79additionalProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/interrupt-controller/arm-gic.h>
84    #include <dt-bindings/clock/mt8173-clk.h>
85    #include <dt-bindings/power/mt8173-power.h>
86    #include <dt-bindings/gce/mt8173-gce.h>
87
88    soc {
89        #address-cells = <2>;
90        #size-cells = <2>;
91
92        mutex: mutex@14020000 {
93            compatible = "mediatek,mt8173-disp-mutex";
94            reg = <0 0x14020000 0 0x1000>;
95            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
96            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
97            clocks = <&mmsys CLK_MM_MUTEX_32K>;
98            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
99                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
100        };
101    };
102