1*fc5a643fSAlexandre Mergnat# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fc5a643fSAlexandre Mergnat%YAML 1.2 3*fc5a643fSAlexandre Mergnat--- 4*fc5a643fSAlexandre Mergnat$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# 5*fc5a643fSAlexandre Mergnat$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fc5a643fSAlexandre Mergnat 7*fc5a643fSAlexandre Mergnattitle: Mediatek PMIC Wrapper 8*fc5a643fSAlexandre Mergnat 9*fc5a643fSAlexandre Mergnatmaintainers: 10*fc5a643fSAlexandre Mergnat - Flora Fu <flora.fu@mediatek.com> 11*fc5a643fSAlexandre Mergnat - Alexandre Mergnat <amergnat@baylibre.com> 12*fc5a643fSAlexandre Mergnat 13*fc5a643fSAlexandre Mergnatdescription: 14*fc5a643fSAlexandre Mergnat On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface 15*fc5a643fSAlexandre Mergnat is not directly visible to the CPU, but only through the PMIC wrapper 16*fc5a643fSAlexandre Mergnat inside the SoC. The communication between the SoC and the PMIC can 17*fc5a643fSAlexandre Mergnat optionally be encrypted. Also a non standard Dual IO SPI mode can be 18*fc5a643fSAlexandre Mergnat used to increase speed. 19*fc5a643fSAlexandre Mergnat 20*fc5a643fSAlexandre Mergnat IP Pairing 21*fc5a643fSAlexandre Mergnat 22*fc5a643fSAlexandre Mergnat On MT8135 the pins of some SoC internal peripherals can be on the PMIC. 23*fc5a643fSAlexandre Mergnat The signals of these pins are routed over the SPI bus using the pwrap 24*fc5a643fSAlexandre Mergnat bridge. In the binding description below the properties needed for bridging 25*fc5a643fSAlexandre Mergnat are marked with "IP Pairing". These are optional on SoCs which do not support 26*fc5a643fSAlexandre Mergnat IP Pairing 27*fc5a643fSAlexandre Mergnat 28*fc5a643fSAlexandre Mergnatproperties: 29*fc5a643fSAlexandre Mergnat compatible: 30*fc5a643fSAlexandre Mergnat oneOf: 31*fc5a643fSAlexandre Mergnat - items: 32*fc5a643fSAlexandre Mergnat - enum: 33*fc5a643fSAlexandre Mergnat - mediatek,mt2701-pwrap 34*fc5a643fSAlexandre Mergnat - mediatek,mt6765-pwrap 35*fc5a643fSAlexandre Mergnat - mediatek,mt6779-pwrap 36*fc5a643fSAlexandre Mergnat - mediatek,mt6797-pwrap 37*fc5a643fSAlexandre Mergnat - mediatek,mt6873-pwrap 38*fc5a643fSAlexandre Mergnat - mediatek,mt7622-pwrap 39*fc5a643fSAlexandre Mergnat - mediatek,mt8135-pwrap 40*fc5a643fSAlexandre Mergnat - mediatek,mt8173-pwrap 41*fc5a643fSAlexandre Mergnat - mediatek,mt8183-pwrap 42*fc5a643fSAlexandre Mergnat - mediatek,mt8186-pwrap 43*fc5a643fSAlexandre Mergnat - mediatek,mt8188-pwrap 44*fc5a643fSAlexandre Mergnat - mediatek,mt8195-pwrap 45*fc5a643fSAlexandre Mergnat - mediatek,mt8365-pwrap 46*fc5a643fSAlexandre Mergnat - mediatek,mt8516-pwrap 47*fc5a643fSAlexandre Mergnat - items: 48*fc5a643fSAlexandre Mergnat - enum: 49*fc5a643fSAlexandre Mergnat - mediatek,mt8186-pwrap 50*fc5a643fSAlexandre Mergnat - mediatek,mt8195-pwrap 51*fc5a643fSAlexandre Mergnat - const: syscon 52*fc5a643fSAlexandre Mergnat 53*fc5a643fSAlexandre Mergnat reg: 54*fc5a643fSAlexandre Mergnat minItems: 1 55*fc5a643fSAlexandre Mergnat items: 56*fc5a643fSAlexandre Mergnat - description: PMIC wrapper registers 57*fc5a643fSAlexandre Mergnat - description: IP pairing registers 58*fc5a643fSAlexandre Mergnat 59*fc5a643fSAlexandre Mergnat reg-names: 60*fc5a643fSAlexandre Mergnat minItems: 1 61*fc5a643fSAlexandre Mergnat items: 62*fc5a643fSAlexandre Mergnat - const: pwrap 63*fc5a643fSAlexandre Mergnat - const: pwrap-bridge 64*fc5a643fSAlexandre Mergnat 65*fc5a643fSAlexandre Mergnat interrupts: 66*fc5a643fSAlexandre Mergnat maxItems: 1 67*fc5a643fSAlexandre Mergnat 68*fc5a643fSAlexandre Mergnat clocks: 69*fc5a643fSAlexandre Mergnat minItems: 2 70*fc5a643fSAlexandre Mergnat items: 71*fc5a643fSAlexandre Mergnat - description: SPI bus clock 72*fc5a643fSAlexandre Mergnat - description: Main module clock 73*fc5a643fSAlexandre Mergnat - description: System module clock 74*fc5a643fSAlexandre Mergnat - description: Timer module clock 75*fc5a643fSAlexandre Mergnat 76*fc5a643fSAlexandre Mergnat clock-names: 77*fc5a643fSAlexandre Mergnat minItems: 2 78*fc5a643fSAlexandre Mergnat items: 79*fc5a643fSAlexandre Mergnat - const: spi 80*fc5a643fSAlexandre Mergnat - const: wrap 81*fc5a643fSAlexandre Mergnat - const: sys 82*fc5a643fSAlexandre Mergnat - const: tmr 83*fc5a643fSAlexandre Mergnat 84*fc5a643fSAlexandre Mergnat resets: 85*fc5a643fSAlexandre Mergnat minItems: 1 86*fc5a643fSAlexandre Mergnat items: 87*fc5a643fSAlexandre Mergnat - description: PMIC wrapper reset 88*fc5a643fSAlexandre Mergnat - description: IP pairing reset 89*fc5a643fSAlexandre Mergnat 90*fc5a643fSAlexandre Mergnat reset-names: 91*fc5a643fSAlexandre Mergnat minItems: 1 92*fc5a643fSAlexandre Mergnat items: 93*fc5a643fSAlexandre Mergnat - const: pwrap 94*fc5a643fSAlexandre Mergnat - const: pwrap-bridge 95*fc5a643fSAlexandre Mergnat 96*fc5a643fSAlexandre Mergnat pmic: 97*fc5a643fSAlexandre Mergnat type: object 98*fc5a643fSAlexandre Mergnat 99*fc5a643fSAlexandre Mergnatrequired: 100*fc5a643fSAlexandre Mergnat - compatible 101*fc5a643fSAlexandre Mergnat - reg 102*fc5a643fSAlexandre Mergnat - reg-names 103*fc5a643fSAlexandre Mergnat - interrupts 104*fc5a643fSAlexandre Mergnat - clocks 105*fc5a643fSAlexandre Mergnat - clock-names 106*fc5a643fSAlexandre Mergnat 107*fc5a643fSAlexandre MergnatdependentRequired: 108*fc5a643fSAlexandre Mergnat resets: [reset-names] 109*fc5a643fSAlexandre Mergnat 110*fc5a643fSAlexandre MergnatallOf: 111*fc5a643fSAlexandre Mergnat - if: 112*fc5a643fSAlexandre Mergnat properties: 113*fc5a643fSAlexandre Mergnat compatible: 114*fc5a643fSAlexandre Mergnat contains: 115*fc5a643fSAlexandre Mergnat const: mediatek,mt8365-pwrap 116*fc5a643fSAlexandre Mergnat then: 117*fc5a643fSAlexandre Mergnat properties: 118*fc5a643fSAlexandre Mergnat clocks: 119*fc5a643fSAlexandre Mergnat minItems: 4 120*fc5a643fSAlexandre Mergnat 121*fc5a643fSAlexandre Mergnat clock-names: 122*fc5a643fSAlexandre Mergnat minItems: 4 123*fc5a643fSAlexandre Mergnat 124*fc5a643fSAlexandre MergnatadditionalProperties: false 125*fc5a643fSAlexandre Mergnat 126*fc5a643fSAlexandre Mergnatexamples: 127*fc5a643fSAlexandre Mergnat - | 128*fc5a643fSAlexandre Mergnat #include <dt-bindings/interrupt-controller/irq.h> 129*fc5a643fSAlexandre Mergnat #include <dt-bindings/interrupt-controller/arm-gic.h> 130*fc5a643fSAlexandre Mergnat #include <dt-bindings/reset/mt8135-resets.h> 131*fc5a643fSAlexandre Mergnat 132*fc5a643fSAlexandre Mergnat soc { 133*fc5a643fSAlexandre Mergnat #address-cells = <2>; 134*fc5a643fSAlexandre Mergnat #size-cells = <2>; 135*fc5a643fSAlexandre Mergnat pwrap@1000f000 { 136*fc5a643fSAlexandre Mergnat compatible = "mediatek,mt8135-pwrap"; 137*fc5a643fSAlexandre Mergnat reg = <0 0x1000f000 0 0x1000>, 138*fc5a643fSAlexandre Mergnat <0 0x11017000 0 0x1000>; 139*fc5a643fSAlexandre Mergnat reg-names = "pwrap", "pwrap-bridge"; 140*fc5a643fSAlexandre Mergnat interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 141*fc5a643fSAlexandre Mergnat clocks = <&clk26m>, <&clk26m>; 142*fc5a643fSAlexandre Mergnat clock-names = "spi", "wrap"; 143*fc5a643fSAlexandre Mergnat resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, 144*fc5a643fSAlexandre Mergnat <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; 145*fc5a643fSAlexandre Mergnat reset-names = "pwrap", "pwrap-bridge"; 146*fc5a643fSAlexandre Mergnat }; 147*fc5a643fSAlexandre Mergnat }; 148