1fc5a643fSAlexandre Mergnat# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2fc5a643fSAlexandre Mergnat%YAML 1.2 3fc5a643fSAlexandre Mergnat--- 4fc5a643fSAlexandre Mergnat$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# 5fc5a643fSAlexandre Mergnat$schema: http://devicetree.org/meta-schemas/core.yaml# 6fc5a643fSAlexandre Mergnat 7fc5a643fSAlexandre Mergnattitle: Mediatek PMIC Wrapper 8fc5a643fSAlexandre Mergnat 9fc5a643fSAlexandre Mergnatmaintainers: 10fc5a643fSAlexandre Mergnat - Flora Fu <flora.fu@mediatek.com> 11fc5a643fSAlexandre Mergnat - Alexandre Mergnat <amergnat@baylibre.com> 12fc5a643fSAlexandre Mergnat 13fc5a643fSAlexandre Mergnatdescription: 14fc5a643fSAlexandre Mergnat On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface 15fc5a643fSAlexandre Mergnat is not directly visible to the CPU, but only through the PMIC wrapper 16fc5a643fSAlexandre Mergnat inside the SoC. The communication between the SoC and the PMIC can 17fc5a643fSAlexandre Mergnat optionally be encrypted. Also a non standard Dual IO SPI mode can be 18fc5a643fSAlexandre Mergnat used to increase speed. 19fc5a643fSAlexandre Mergnat 20fc5a643fSAlexandre Mergnat IP Pairing 21fc5a643fSAlexandre Mergnat 22fc5a643fSAlexandre Mergnat On MT8135 the pins of some SoC internal peripherals can be on the PMIC. 23fc5a643fSAlexandre Mergnat The signals of these pins are routed over the SPI bus using the pwrap 24fc5a643fSAlexandre Mergnat bridge. In the binding description below the properties needed for bridging 25fc5a643fSAlexandre Mergnat are marked with "IP Pairing". These are optional on SoCs which do not support 26fc5a643fSAlexandre Mergnat IP Pairing 27fc5a643fSAlexandre Mergnat 28fc5a643fSAlexandre Mergnatproperties: 29fc5a643fSAlexandre Mergnat compatible: 30fc5a643fSAlexandre Mergnat oneOf: 31fc5a643fSAlexandre Mergnat - items: 32fc5a643fSAlexandre Mergnat - enum: 33fc5a643fSAlexandre Mergnat - mediatek,mt2701-pwrap 34fc5a643fSAlexandre Mergnat - mediatek,mt6765-pwrap 35fc5a643fSAlexandre Mergnat - mediatek,mt6779-pwrap 36*e829f1fcSAngeloGioacchino Del Regno - mediatek,mt6795-pwrap 37fc5a643fSAlexandre Mergnat - mediatek,mt6797-pwrap 38fc5a643fSAlexandre Mergnat - mediatek,mt6873-pwrap 39fc5a643fSAlexandre Mergnat - mediatek,mt7622-pwrap 40fc5a643fSAlexandre Mergnat - mediatek,mt8135-pwrap 41fc5a643fSAlexandre Mergnat - mediatek,mt8173-pwrap 42fc5a643fSAlexandre Mergnat - mediatek,mt8183-pwrap 43fc5a643fSAlexandre Mergnat - mediatek,mt8186-pwrap 44fc5a643fSAlexandre Mergnat - mediatek,mt8188-pwrap 45fc5a643fSAlexandre Mergnat - mediatek,mt8195-pwrap 46fc5a643fSAlexandre Mergnat - mediatek,mt8365-pwrap 47fc5a643fSAlexandre Mergnat - mediatek,mt8516-pwrap 48fc5a643fSAlexandre Mergnat - items: 49fc5a643fSAlexandre Mergnat - enum: 50fc5a643fSAlexandre Mergnat - mediatek,mt8186-pwrap 51fc5a643fSAlexandre Mergnat - mediatek,mt8195-pwrap 52fc5a643fSAlexandre Mergnat - const: syscon 53fc5a643fSAlexandre Mergnat 54fc5a643fSAlexandre Mergnat reg: 55fc5a643fSAlexandre Mergnat minItems: 1 56fc5a643fSAlexandre Mergnat items: 57fc5a643fSAlexandre Mergnat - description: PMIC wrapper registers 58fc5a643fSAlexandre Mergnat - description: IP pairing registers 59fc5a643fSAlexandre Mergnat 60fc5a643fSAlexandre Mergnat reg-names: 61fc5a643fSAlexandre Mergnat minItems: 1 62fc5a643fSAlexandre Mergnat items: 63fc5a643fSAlexandre Mergnat - const: pwrap 64fc5a643fSAlexandre Mergnat - const: pwrap-bridge 65fc5a643fSAlexandre Mergnat 66fc5a643fSAlexandre Mergnat interrupts: 67fc5a643fSAlexandre Mergnat maxItems: 1 68fc5a643fSAlexandre Mergnat 69fc5a643fSAlexandre Mergnat clocks: 70fc5a643fSAlexandre Mergnat minItems: 2 71fc5a643fSAlexandre Mergnat items: 72fc5a643fSAlexandre Mergnat - description: SPI bus clock 73fc5a643fSAlexandre Mergnat - description: Main module clock 74fc5a643fSAlexandre Mergnat - description: System module clock 75fc5a643fSAlexandre Mergnat - description: Timer module clock 76fc5a643fSAlexandre Mergnat 77fc5a643fSAlexandre Mergnat clock-names: 78fc5a643fSAlexandre Mergnat minItems: 2 79fc5a643fSAlexandre Mergnat items: 80fc5a643fSAlexandre Mergnat - const: spi 81fc5a643fSAlexandre Mergnat - const: wrap 82fc5a643fSAlexandre Mergnat - const: sys 83fc5a643fSAlexandre Mergnat - const: tmr 84fc5a643fSAlexandre Mergnat 85fc5a643fSAlexandre Mergnat resets: 86fc5a643fSAlexandre Mergnat minItems: 1 87fc5a643fSAlexandre Mergnat items: 88fc5a643fSAlexandre Mergnat - description: PMIC wrapper reset 89fc5a643fSAlexandre Mergnat - description: IP pairing reset 90fc5a643fSAlexandre Mergnat 91fc5a643fSAlexandre Mergnat reset-names: 92fc5a643fSAlexandre Mergnat minItems: 1 93fc5a643fSAlexandre Mergnat items: 94fc5a643fSAlexandre Mergnat - const: pwrap 95fc5a643fSAlexandre Mergnat - const: pwrap-bridge 96fc5a643fSAlexandre Mergnat 97fc5a643fSAlexandre Mergnat pmic: 98fc5a643fSAlexandre Mergnat type: object 99fc5a643fSAlexandre Mergnat 100fc5a643fSAlexandre Mergnatrequired: 101fc5a643fSAlexandre Mergnat - compatible 102fc5a643fSAlexandre Mergnat - reg 103fc5a643fSAlexandre Mergnat - reg-names 104fc5a643fSAlexandre Mergnat - interrupts 105fc5a643fSAlexandre Mergnat - clocks 106fc5a643fSAlexandre Mergnat - clock-names 107fc5a643fSAlexandre Mergnat 108fc5a643fSAlexandre MergnatdependentRequired: 109fc5a643fSAlexandre Mergnat resets: [reset-names] 110fc5a643fSAlexandre Mergnat 111fc5a643fSAlexandre MergnatallOf: 112fc5a643fSAlexandre Mergnat - if: 113fc5a643fSAlexandre Mergnat properties: 114fc5a643fSAlexandre Mergnat compatible: 115fc5a643fSAlexandre Mergnat contains: 116fc5a643fSAlexandre Mergnat const: mediatek,mt8365-pwrap 117fc5a643fSAlexandre Mergnat then: 118fc5a643fSAlexandre Mergnat properties: 119fc5a643fSAlexandre Mergnat clocks: 120fc5a643fSAlexandre Mergnat minItems: 4 121fc5a643fSAlexandre Mergnat 122fc5a643fSAlexandre Mergnat clock-names: 123fc5a643fSAlexandre Mergnat minItems: 4 124fc5a643fSAlexandre Mergnat 125fc5a643fSAlexandre MergnatadditionalProperties: false 126fc5a643fSAlexandre Mergnat 127fc5a643fSAlexandre Mergnatexamples: 128fc5a643fSAlexandre Mergnat - | 129fc5a643fSAlexandre Mergnat #include <dt-bindings/interrupt-controller/irq.h> 130fc5a643fSAlexandre Mergnat #include <dt-bindings/interrupt-controller/arm-gic.h> 131fc5a643fSAlexandre Mergnat #include <dt-bindings/reset/mt8135-resets.h> 132fc5a643fSAlexandre Mergnat 133fc5a643fSAlexandre Mergnat soc { 134fc5a643fSAlexandre Mergnat #address-cells = <2>; 135fc5a643fSAlexandre Mergnat #size-cells = <2>; 136fc5a643fSAlexandre Mergnat pwrap@1000f000 { 137fc5a643fSAlexandre Mergnat compatible = "mediatek,mt8135-pwrap"; 138fc5a643fSAlexandre Mergnat reg = <0 0x1000f000 0 0x1000>, 139fc5a643fSAlexandre Mergnat <0 0x11017000 0 0x1000>; 140fc5a643fSAlexandre Mergnat reg-names = "pwrap", "pwrap-bridge"; 141fc5a643fSAlexandre Mergnat interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 142fc5a643fSAlexandre Mergnat clocks = <&clk26m>, <&clk26m>; 143fc5a643fSAlexandre Mergnat clock-names = "spi", "wrap"; 144fc5a643fSAlexandre Mergnat resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, 145fc5a643fSAlexandre Mergnat <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; 146fc5a643fSAlexandre Mergnat reset-names = "pwrap", "pwrap-bridge"; 147fc5a643fSAlexandre Mergnat }; 148fc5a643fSAlexandre Mergnat }; 149