1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek mutex
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
15  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
16  data path or MDP data path.
17  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
18  the shadow register.
19  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
20  For a description of the MMSYS_CONFIG binding, see
21  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
22  for details.
23
24properties:
25  compatible:
26    enum:
27      - mediatek,mt2701-disp-mutex
28      - mediatek,mt2712-disp-mutex
29      - mediatek,mt6795-disp-mutex
30      - mediatek,mt8167-disp-mutex
31      - mediatek,mt8173-disp-mutex
32      - mediatek,mt8183-disp-mutex
33      - mediatek,mt8186-disp-mutex
34      - mediatek,mt8186-mdp3-mutex
35      - mediatek,mt8188-disp-mutex
36      - mediatek,mt8192-disp-mutex
37      - mediatek,mt8195-disp-mutex
38      - mediatek,mt8195-vpp-mutex
39
40  reg:
41    maxItems: 1
42
43  interrupts:
44    maxItems: 1
45
46  power-domains:
47    description: A phandle and PM domain specifier as defined by bindings of
48      the power controller specified by phandle. See
49      Documentation/devicetree/bindings/power/power-domain.yaml for details.
50
51  clocks:
52    items:
53      - description: MUTEX Clock
54
55  mediatek,gce-events:
56    description:
57      The event id which is mapping to the specific hardware event signal
58      to gce. The event id is defined in the gce header
59      include/dt-bindings/gce/<chip>-gce.h of each chips.
60    $ref: /schemas/types.yaml#/definitions/uint32-array
61
62  mediatek,gce-client-reg:
63    $ref: /schemas/types.yaml#/definitions/phandle-array
64    items:
65      items:
66        - description: phandle of GCE
67        - description: GCE subsys id
68        - description: register offset
69        - description: register size
70    description: The register of client driver can be configured by gce with
71      4 arguments defined in this property. Each GCE subsys id is mapping to
72      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
73
74required:
75  - compatible
76  - reg
77  - interrupts
78  - power-domains
79  - clocks
80
81additionalProperties: false
82
83examples:
84  - |
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86    #include <dt-bindings/clock/mt8173-clk.h>
87    #include <dt-bindings/power/mt8173-power.h>
88    #include <dt-bindings/gce/mt8173-gce.h>
89
90    soc {
91        #address-cells = <2>;
92        #size-cells = <2>;
93
94        mutex: mutex@14020000 {
95            compatible = "mediatek,mt8173-disp-mutex";
96            reg = <0 0x14020000 0 0x1000>;
97            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
98            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
99            clocks = <&mmsys CLK_MM_MUTEX_32K>;
100            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
101                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
102        };
103    };
104