159bf87eeSMoudy Ho# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
259bf87eeSMoudy Ho%YAML 1.2
359bf87eeSMoudy Ho---
459bf87eeSMoudy Ho$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml#
559bf87eeSMoudy Ho$schema: http://devicetree.org/meta-schemas/core.yaml#
659bf87eeSMoudy Ho
759bf87eeSMoudy Hotitle: Mediatek mutex
859bf87eeSMoudy Ho
959bf87eeSMoudy Homaintainers:
1059bf87eeSMoudy Ho  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
1159bf87eeSMoudy Ho  - Philipp Zabel <p.zabel@pengutronix.de>
1259bf87eeSMoudy Ho
1359bf87eeSMoudy Hodescription: |
1459bf87eeSMoudy Ho  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
1559bf87eeSMoudy Ho  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
1659bf87eeSMoudy Ho  data path or MDP data path.
1759bf87eeSMoudy Ho  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
1859bf87eeSMoudy Ho  the shadow register.
1959bf87eeSMoudy Ho  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
2059bf87eeSMoudy Ho  For a description of the MMSYS_CONFIG binding, see
2159bf87eeSMoudy Ho  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
2259bf87eeSMoudy Ho  for details.
2359bf87eeSMoudy Ho
2459bf87eeSMoudy Hoproperties:
2559bf87eeSMoudy Ho  compatible:
2659bf87eeSMoudy Ho    enum:
2759bf87eeSMoudy Ho      - mediatek,mt2701-disp-mutex
2859bf87eeSMoudy Ho      - mediatek,mt2712-disp-mutex
29*f3894f96SAngeloGioacchino Del Regno      - mediatek,mt6795-disp-mutex
3059bf87eeSMoudy Ho      - mediatek,mt8167-disp-mutex
3159bf87eeSMoudy Ho      - mediatek,mt8173-disp-mutex
3259bf87eeSMoudy Ho      - mediatek,mt8183-disp-mutex
3359bf87eeSMoudy Ho      - mediatek,mt8186-disp-mutex
347c4ddc81SAllen-KH Cheng      - mediatek,mt8186-mdp3-mutex
3559bf87eeSMoudy Ho      - mediatek,mt8192-disp-mutex
3659bf87eeSMoudy Ho      - mediatek,mt8195-disp-mutex
3759bf87eeSMoudy Ho
3859bf87eeSMoudy Ho  reg:
3959bf87eeSMoudy Ho    maxItems: 1
4059bf87eeSMoudy Ho
4159bf87eeSMoudy Ho  interrupts:
4259bf87eeSMoudy Ho    maxItems: 1
4359bf87eeSMoudy Ho
4459bf87eeSMoudy Ho  power-domains:
4559bf87eeSMoudy Ho    description: A phandle and PM domain specifier as defined by bindings of
4659bf87eeSMoudy Ho      the power controller specified by phandle. See
4759bf87eeSMoudy Ho      Documentation/devicetree/bindings/power/power-domain.yaml for details.
4859bf87eeSMoudy Ho
4959bf87eeSMoudy Ho  clocks:
5059bf87eeSMoudy Ho    items:
5159bf87eeSMoudy Ho      - description: MUTEX Clock
5259bf87eeSMoudy Ho
5359bf87eeSMoudy Ho  mediatek,gce-events:
5459bf87eeSMoudy Ho    description:
5559bf87eeSMoudy Ho      The event id which is mapping to the specific hardware event signal
5659bf87eeSMoudy Ho      to gce. The event id is defined in the gce header
5759bf87eeSMoudy Ho      include/dt-bindings/gce/<chip>-gce.h of each chips.
5859bf87eeSMoudy Ho    $ref: /schemas/types.yaml#/definitions/uint32-array
5959bf87eeSMoudy Ho
60e3b6b5a9SMoudy Ho  mediatek,gce-client-reg:
61e3b6b5a9SMoudy Ho    $ref: /schemas/types.yaml#/definitions/phandle-array
62e3b6b5a9SMoudy Ho    items:
63e3b6b5a9SMoudy Ho      items:
64e3b6b5a9SMoudy Ho        - description: phandle of GCE
65e3b6b5a9SMoudy Ho        - description: GCE subsys id
66e3b6b5a9SMoudy Ho        - description: register offset
67e3b6b5a9SMoudy Ho        - description: register size
68e3b6b5a9SMoudy Ho    description: The register of client driver can be configured by gce with
69e3b6b5a9SMoudy Ho      4 arguments defined in this property. Each GCE subsys id is mapping to
70e3b6b5a9SMoudy Ho      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
71e3b6b5a9SMoudy Ho
7259bf87eeSMoudy Horequired:
7359bf87eeSMoudy Ho  - compatible
7459bf87eeSMoudy Ho  - reg
7559bf87eeSMoudy Ho  - interrupts
7659bf87eeSMoudy Ho  - power-domains
7759bf87eeSMoudy Ho  - clocks
7859bf87eeSMoudy Ho
7959bf87eeSMoudy HoadditionalProperties: false
8059bf87eeSMoudy Ho
8159bf87eeSMoudy Hoexamples:
8259bf87eeSMoudy Ho  - |
8359bf87eeSMoudy Ho    #include <dt-bindings/interrupt-controller/arm-gic.h>
8459bf87eeSMoudy Ho    #include <dt-bindings/clock/mt8173-clk.h>
8559bf87eeSMoudy Ho    #include <dt-bindings/power/mt8173-power.h>
8659bf87eeSMoudy Ho    #include <dt-bindings/gce/mt8173-gce.h>
8759bf87eeSMoudy Ho
8859bf87eeSMoudy Ho    soc {
8959bf87eeSMoudy Ho        #address-cells = <2>;
9059bf87eeSMoudy Ho        #size-cells = <2>;
9159bf87eeSMoudy Ho
9259bf87eeSMoudy Ho        mutex: mutex@14020000 {
9359bf87eeSMoudy Ho            compatible = "mediatek,mt8173-disp-mutex";
9459bf87eeSMoudy Ho            reg = <0 0x14020000 0 0x1000>;
9559bf87eeSMoudy Ho            interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
9659bf87eeSMoudy Ho            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
9759bf87eeSMoudy Ho            clocks = <&mmsys CLK_MM_MUTEX_32K>;
9859bf87eeSMoudy Ho            mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
9959bf87eeSMoudy Ho                                  <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
10059bf87eeSMoudy Ho        };
10159bf87eeSMoudy Ho    };
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