1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/imx/fsl,imx93-src.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX93 System Reset Controller 8 9maintainers: 10 - Peng Fan <peng.fan@nxp.com> 11 12description: | 13 The System Reset Controller (SRC) is responsible for the generation of 14 all the system reset signals and boot argument latching. 15 16 Its main functions are as follows, 17 - Deals with all global system reset sources from other modules, 18 and generates global system reset. 19 - Responsible for power gating of MIXs (Slices) and their memory 20 low power control. 21 22properties: 23 compatible: 24 items: 25 - const: fsl,imx93-src 26 - const: syscon 27 28 reg: 29 maxItems: 1 30 31 ranges: true 32 33 '#address-cells': 34 const: 1 35 36 '#size-cells': 37 const: 1 38 39patternProperties: 40 "power-domain@[0-9a-f]+$": 41 type: object 42 additionalProperties: false 43 44 properties: 45 compatible: 46 items: 47 - const: fsl,imx93-src-slice 48 49 '#power-domain-cells': 50 const: 0 51 52 reg: 53 items: 54 - description: mix slice register region 55 - description: mem slice register region 56 57 clocks: 58 description: | 59 A number of phandles to clocks that need to be enabled 60 during domain power-up sequencing to ensure reset 61 propagation into devices located inside this power domain. 62 minItems: 1 63 maxItems: 5 64 65 required: 66 - compatible 67 - '#power-domain-cells' 68 - reg 69 70required: 71 - compatible 72 - reg 73 - ranges 74 - '#address-cells' 75 - '#size-cells' 76 77additionalProperties: false 78 79examples: 80 - | 81 #include <dt-bindings/clock/imx93-clock.h> 82 83 system-controller@44460000 { 84 compatible = "fsl,imx93-src", "syscon"; 85 reg = <0x44460000 0x10000>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 90 mediamix: power-domain@0 { 91 compatible = "fsl,imx93-src-slice"; 92 reg = <0x44462400 0x400>, <0x44465800 0x400>; 93 #power-domain-cells = <0>; 94 clocks = <&clk IMX93_CLK_MEDIA_AXI>, 95 <&clk IMX93_CLK_MEDIA_APB>; 96 }; 97 }; 98