1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX8MM VPU blk-ctrl 8 9maintainers: 10 - Lucas Stach <l.stach@pengutronix.de> 11 12description: 13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the VPU peripherals 15 located in the VPU domain of the SoC. 16 17properties: 18 compatible: 19 items: 20 - const: fsl,imx8mm-vpu-blk-ctrl 21 - const: syscon 22 23 reg: 24 maxItems: 1 25 26 '#power-domain-cells': 27 const: 1 28 29 power-domains: 30 maxItems: 4 31 32 power-domain-names: 33 items: 34 - const: bus 35 - const: g1 36 - const: g2 37 - const: h1 38 39 clocks: 40 maxItems: 3 41 42 clock-names: 43 items: 44 - const: g1 45 - const: g2 46 - const: h1 47 48 interconnects: 49 items: 50 - description: G1 decoder interconnect 51 - description: G2 decoder interconnect 52 - description: H1 encoder power domain 53 54 interconnect-names: 55 items: 56 - const: g1 57 - const: g2 58 - const: h1 59 60required: 61 - compatible 62 - reg 63 - power-domains 64 - power-domain-names 65 - clocks 66 - clock-names 67 68additionalProperties: false 69 70examples: 71 - | 72 #include <dt-bindings/clock/imx8mm-clock.h> 73 #include <dt-bindings/power/imx8mm-power.h> 74 75 vpu_blk_ctrl: blk-ctrl@38330000 { 76 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 77 reg = <0x38330000 0x100>; 78 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 79 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 80 power-domain-names = "bus", "g1", "g2", "h1"; 81 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 82 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 83 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 84 clock-names = "g1", "g2", "h1"; 85 #power-domain-cells = <1>; 86 }; 87