1*ac6583f5SMichael Walle# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*ac6583f5SMichael Walle%YAML 1.2
3*ac6583f5SMichael Walle---
4*ac6583f5SMichael Walle$id: http://devicetree.org/schemas/soc/fsl/fsl,layerscape-dcfg.yaml#
5*ac6583f5SMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ac6583f5SMichael Walle
7*ac6583f5SMichael Walletitle: Freescale Layerscape Device Configuration Unit
8*ac6583f5SMichael Walle
9*ac6583f5SMichael Wallemaintainers:
10*ac6583f5SMichael Walle  - Shawn Guo <shawnguo@kernel.org>
11*ac6583f5SMichael Walle  - Li Yang <leoyang.li@nxp.com>
12*ac6583f5SMichael Walle
13*ac6583f5SMichael Walledescription: |
14*ac6583f5SMichael Walle  DCFG is the device configuration unit, that provides general purpose
15*ac6583f5SMichael Walle  configuration and status for the device. Such as setting the secondary
16*ac6583f5SMichael Walle  core start address and release the secondary core from holdoff and
17*ac6583f5SMichael Walle  startup.
18*ac6583f5SMichael Walle
19*ac6583f5SMichael Walleproperties:
20*ac6583f5SMichael Walle  compatible:
21*ac6583f5SMichael Walle    oneOf:
22*ac6583f5SMichael Walle      - items:
23*ac6583f5SMichael Walle          - enum:
24*ac6583f5SMichael Walle              - fsl,ls1012a-dcfg
25*ac6583f5SMichael Walle              - fsl,ls1021a-dcfg
26*ac6583f5SMichael Walle              - fsl,ls1043a-dcfg
27*ac6583f5SMichael Walle              - fsl,ls1046a-dcfg
28*ac6583f5SMichael Walle              - fsl,ls1088a-dcfg
29*ac6583f5SMichael Walle              - fsl,ls2080a-dcfg
30*ac6583f5SMichael Walle              - fsl,lx2160a-dcfg
31*ac6583f5SMichael Walle          - const: syscon
32*ac6583f5SMichael Walle
33*ac6583f5SMichael Walle      - items:
34*ac6583f5SMichael Walle          - enum:
35*ac6583f5SMichael Walle              - fsl,ls1028a-dcfg
36*ac6583f5SMichael Walle          - const: syscon
37*ac6583f5SMichael Walle          - const: simple-mfd
38*ac6583f5SMichael Walle
39*ac6583f5SMichael Walle  reg:
40*ac6583f5SMichael Walle    maxItems: 1
41*ac6583f5SMichael Walle
42*ac6583f5SMichael Walle  little-endian: true
43*ac6583f5SMichael Walle  big-endian: true
44*ac6583f5SMichael Walle
45*ac6583f5SMichael Walle  '#address-cells':
46*ac6583f5SMichael Walle    const: 1
47*ac6583f5SMichael Walle
48*ac6583f5SMichael Walle  '#size-cells':
49*ac6583f5SMichael Walle    const: 1
50*ac6583f5SMichael Walle
51*ac6583f5SMichael Walle  ranges: true
52*ac6583f5SMichael Walle
53*ac6583f5SMichael WallepatternProperties:
54*ac6583f5SMichael Walle  "^clock-controller@[0-9a-z]+$":
55*ac6583f5SMichael Walle    $ref: /schemas/clock/fsl,flexspi-clock.yaml#
56*ac6583f5SMichael Walle
57*ac6583f5SMichael Wallerequired:
58*ac6583f5SMichael Walle  - compatible
59*ac6583f5SMichael Walle  - reg
60*ac6583f5SMichael Walle
61*ac6583f5SMichael WalleadditionalProperties: false
62*ac6583f5SMichael Walle
63*ac6583f5SMichael Walleexamples:
64*ac6583f5SMichael Walle  - |
65*ac6583f5SMichael Walle    syscon@1ee0000 {
66*ac6583f5SMichael Walle        compatible = "fsl,ls1021a-dcfg", "syscon";
67*ac6583f5SMichael Walle        reg = <0x1ee0000 0x10000>;
68*ac6583f5SMichael Walle    };
69