1Device Tree bindings for Marvell PMU
2
3Required properties:
4 - compatible: value should be "marvell,dove-pmu".
5    May also include "simple-bus" if there are child devices, in which
6    case the ranges node is required.
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
10    interrupt controller.
11 - #interrupt-cells: must be 1.
12 - #reset-cells: must be 1.
13 - domains: sub-node containing domain descriptions
14
15Optional properties:
16 - ranges: defines the address mapping for child devices, as per the
17   standard property of this name.  Required when compatible includes
18   "simple-bus".
19
20Power domain descriptions are listed as child nodes of the "domains"
21sub-node.  Each domain has the following properties:
22
23Required properties:
24 - #power-domain-cells: must be 0.
25
26Optional properties:
27 - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
28 - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
29 - resets: points to the reset manager (PMU node) and reset index.
30
31Example:
32
33	pmu: power-management@d0000 {
34		compatible = "marvell,dove-pmu";
35		reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
36		interrupts = <33>;
37		interrupt-controller;
38		#interrupt-cells = <1>;
39		#reset-cells = <1>;
40
41		domains {
42			vpu_domain: vpu-domain {
43				#power-domain-cells = <0>;
44				marvell,pmu_pwr_mask = <0x00000008>;
45				marvell,pmu_iso_mask = <0x00000001>;
46				resets = <&pmu 16>;
47			};
48
49			gpu_domain: gpu-domain {
50				#power-domain-cells = <0>;
51				marvell,pmu_pwr_mask = <0x00000004>;
52				marvell,pmu_iso_mask = <0x00000002>;
53				resets = <&pmu 18>;
54			};
55		};
56	};
57