1a7e0eddeSTony Prisk* VIA VT8500 and WonderMedia WM8xxx UART Controller
2a7e0eddeSTony Prisk
3a7e0eddeSTony PriskRequired properties:
4ae382735SAlexey Charkov- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
5ae382735SAlexey Charkov	including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
6a7e0eddeSTony Prisk
7a7e0eddeSTony Prisk- reg: base physical address of the controller and length of memory mapped
8a7e0eddeSTony Prisk	region.
9a7e0eddeSTony Prisk
10a7e0eddeSTony Prisk- interrupts: hardware interrupt number
11a7e0eddeSTony Prisk
12a7e0eddeSTony Prisk- clocks: shall be the input parent clock phandle for the clock. This should
13a7e0eddeSTony Prisk	be the 24Mhz reference clock.
14a7e0eddeSTony Prisk
15a7e0eddeSTony PriskAliases may be defined to ensure the correct ordering of the uarts.
16a7e0eddeSTony Prisk
17a7e0eddeSTony PriskExample:
18a7e0eddeSTony Prisk	aliases {
19a7e0eddeSTony Prisk		serial0 = &uart0;
20a7e0eddeSTony Prisk	};
21a7e0eddeSTony Prisk
22a7e0eddeSTony Prisk	uart0: serial@d8200000 {
23a7e0eddeSTony Prisk		compatible = "via,vt8500-uart";
24a7e0eddeSTony Prisk		reg = <0xd8200000 0x1040>;
25a7e0eddeSTony Prisk		interrupts = <32>;
26a7e0eddeSTony Prisk		clocks = <&clkuart0>;
27a7e0eddeSTony Prisk	};
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