1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/serial/sifive-serial.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SiFive asynchronous serial interface (UART) 8 9maintainers: 10 - Pragnesh Patel <pragnesh.patel@sifive.com> 11 - Paul Walmsley <paul.walmsley@sifive.com> 12 - Palmer Dabbelt <palmer@sifive.com> 13 14allOf: 15 - $ref: /schemas/serial.yaml# 16 17properties: 18 compatible: 19 items: 20 - enum: 21 - sifive,fu540-c000-uart 22 - sifive,fu740-c000-uart 23 - const: sifive,uart0 24 25 description: 26 Should be something similar to "sifive,<chip>-uart" 27 for the UART as integrated on a particular chip, 28 and "sifive,uart<version>" for the general UART IP 29 block programming model. 30 31 UART HDL that corresponds to the IP block version 32 numbers can be found here - 33 34 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart 35 36 reg: 37 maxItems: 1 38 39 interrupts: 40 maxItems: 1 41 42 clocks: 43 maxItems: 1 44 45required: 46 - compatible 47 - reg 48 - interrupts 49 - clocks 50 51additionalProperties: false 52 53examples: 54 - | 55 #include <dt-bindings/clock/sifive-fu540-prci.h> 56 serial@10010000 { 57 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 58 interrupt-parent = <&plic0>; 59 interrupts = <80>; 60 reg = <0x10010000 0x1000>; 61 clocks = <&prci PRCI_CLK_TLCLK>; 62 }; 63 64... 65