1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/serial/renesas,sci.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Serial Communication Interface
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12allOf:
13  - $ref: serial.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - renesas,r9a07g044-sci     # RZ/G2{L,LC}
21              - renesas,r9a07g054-sci     # RZ/V2L
22          - const: renesas,sci            # generic SCI compatible UART
23
24      - items:
25          - const: renesas,sci            # generic SCI compatible UART
26
27  reg:
28    maxItems: 1
29
30  interrupts:
31    items:
32      - description: Error interrupt
33      - description: Receive buffer full interrupt
34      - description: Transmit buffer empty interrupt
35      - description: Transmit end interrupt
36
37  interrupt-names:
38    items:
39      - const: eri
40      - const: rxi
41      - const: txi
42      - const: tei
43
44  clocks:
45    minItems: 1
46    maxItems: 2
47
48  clock-names:
49    minItems: 1
50    maxItems: 2
51    items:
52      enum:
53        - fck # UART functional clock
54        - sck # optional external clock input
55
56  uart-has-rtscts: false
57
58required:
59  - compatible
60  - reg
61  - interrupts
62  - clocks
63  - clock-names
64
65if:
66  properties:
67    compatible:
68      contains:
69        enum:
70          - renesas,r9a07g044-sci
71          - renesas,r9a07g054-sci
72then:
73  properties:
74    resets:
75      maxItems: 1
76
77    power-domains:
78      maxItems: 1
79
80  required:
81    - resets
82    - power-domains
83
84unevaluatedProperties: false
85
86examples:
87  - |
88    #include <dt-bindings/clock/r9a07g044-cpg.h>
89    #include <dt-bindings/interrupt-controller/arm-gic.h>
90
91    aliases {
92            serial0 = &sci0;
93    };
94
95    sci0: serial@1004d000 {
96            compatible = "renesas,r9a07g044-sci", "renesas,sci";
97            reg = <0x1004d000 0x400>;
98            interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
99                         <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
100                         <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
101                         <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
102            interrupt-names = "eri", "rxi", "txi", "tei";
103            clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
104            clock-names = "fck";
105            power-domains = <&cpg>;
106            resets = <&cpg R9A07G044_SCI0_RST>;
107    };
108