1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12allOf: 13 - $ref: serial.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - renesas,hscif-r8a7778 # R-Car M1 21 - renesas,hscif-r8a7779 # R-Car H1 22 - const: renesas,rcar-gen1-hscif # R-Car Gen1 23 - const: renesas,hscif # generic HSCIF compatible UART 24 25 - items: 26 - enum: 27 - renesas,hscif-r8a7742 # RZ/G1H 28 - renesas,hscif-r8a7743 # RZ/G1M 29 - renesas,hscif-r8a7744 # RZ/G1N 30 - renesas,hscif-r8a7745 # RZ/G1E 31 - renesas,hscif-r8a77470 # RZ/G1C 32 - renesas,hscif-r8a7790 # R-Car H2 33 - renesas,hscif-r8a7791 # R-Car M2-W 34 - renesas,hscif-r8a7792 # R-Car V2H 35 - renesas,hscif-r8a7793 # R-Car M2-N 36 - renesas,hscif-r8a7794 # R-Car E2 37 - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1 38 - const: renesas,hscif # generic HSCIF compatible UART 39 40 - items: 41 - enum: 42 - renesas,hscif-r8a774a1 # RZ/G2M 43 - renesas,hscif-r8a774b1 # RZ/G2N 44 - renesas,hscif-r8a774c0 # RZ/G2E 45 - renesas,hscif-r8a7795 # R-Car H3 46 - renesas,hscif-r8a7796 # R-Car M3-W 47 - renesas,hscif-r8a77961 # R-Car M3-W+ 48 - renesas,hscif-r8a77965 # R-Car M3-N 49 - renesas,hscif-r8a77970 # R-Car V3M 50 - renesas,hscif-r8a77980 # R-Car V3H 51 - renesas,hscif-r8a77990 # R-Car E3 52 - renesas,hscif-r8a77995 # R-Car D3 53 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 54 - const: renesas,hscif # generic HSCIF compatible UART 55 56 reg: 57 maxItems: 1 58 59 interrupts: 60 maxItems: 1 61 62 clocks: 63 minItems: 1 64 maxItems: 4 65 66 clock-names: 67 minItems: 1 68 maxItems: 4 69 items: 70 enum: 71 - fck # UART functional clock 72 - hsck # optional external clock input 73 - brg_int # optional internal clock source for BRG frequency divider 74 - scif_clk # optional external clock source for BRG frequency divider 75 76 power-domains: 77 maxItems: 1 78 79 resets: 80 maxItems: 1 81 82 dmas: 83 description: 84 Must contain a list of pairs of references to DMA specifiers, one for 85 transmission, and one for reception. 86 87 dma-names: 88 minItems: 2 89 maxItems: 4 90 items: 91 enum: 92 - tx 93 - rx 94 95required: 96 - compatible 97 - reg 98 - interrupts 99 - clocks 100 - clock-names 101 - power-domains 102 103if: 104 properties: 105 compatible: 106 contains: 107 enum: 108 - renesas,rcar-gen2-hscif 109 - renesas,rcar-gen3-hscif 110then: 111 required: 112 - resets 113 114examples: 115 - | 116 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 117 #include <dt-bindings/interrupt-controller/arm-gic.h> 118 #include <dt-bindings/power/r8a7795-sysc.h> 119 aliases { 120 serial1 = &hscif1; 121 }; 122 123 hscif1: serial@e6550000 { 124 compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", 125 "renesas,hscif"; 126 reg = <0xe6550000 96>; 127 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 128 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, 129 <&scif_clk>; 130 clock-names = "fck", "brg_int", "scif_clk"; 131 dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; 132 dma-names = "tx", "rx", "tx", "rx"; 133 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 134 resets = <&cpg 519>; 135 uart-has-rtscts; 136 }; 137