1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/serial/renesas,hscif.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Renesas High Speed Serial Communication Interface with FIFO (HSCIF) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12allOf: 13 - $ref: serial.yaml# 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - renesas,hscif-r8a7778 # R-Car M1 21 - renesas,hscif-r8a7779 # R-Car H1 22 - const: renesas,rcar-gen1-hscif # R-Car Gen1 23 - const: renesas,hscif # generic HSCIF compatible UART 24 25 - items: 26 - enum: 27 - renesas,hscif-r8a7742 # RZ/G1H 28 - renesas,hscif-r8a7743 # RZ/G1M 29 - renesas,hscif-r8a7744 # RZ/G1N 30 - renesas,hscif-r8a7745 # RZ/G1E 31 - renesas,hscif-r8a77470 # RZ/G1C 32 - renesas,hscif-r8a7790 # R-Car H2 33 - renesas,hscif-r8a7791 # R-Car M2-W 34 - renesas,hscif-r8a7792 # R-Car V2H 35 - renesas,hscif-r8a7793 # R-Car M2-N 36 - renesas,hscif-r8a7794 # R-Car E2 37 - const: renesas,rcar-gen2-hscif # R-Car Gen2 and RZ/G1 38 - const: renesas,hscif # generic HSCIF compatible UART 39 40 - items: 41 - enum: 42 - renesas,hscif-r8a774a1 # RZ/G2M 43 - renesas,hscif-r8a774b1 # RZ/G2N 44 - renesas,hscif-r8a774c0 # RZ/G2E 45 - renesas,hscif-r8a774e1 # RZ/G2H 46 - renesas,hscif-r8a7795 # R-Car H3 47 - renesas,hscif-r8a7796 # R-Car M3-W 48 - renesas,hscif-r8a77961 # R-Car M3-W+ 49 - renesas,hscif-r8a77965 # R-Car M3-N 50 - renesas,hscif-r8a77970 # R-Car V3M 51 - renesas,hscif-r8a77980 # R-Car V3H 52 - renesas,hscif-r8a77990 # R-Car E3 53 - renesas,hscif-r8a77995 # R-Car D3 54 - const: renesas,rcar-gen3-hscif # R-Car Gen3 and RZ/G2 55 - const: renesas,hscif # generic HSCIF compatible UART 56 57 - items: 58 - enum: 59 - renesas,hscif-r8a779a0 # R-Car V3U 60 - renesas,hscif-r8a779g0 # R-Car V4H 61 - const: renesas,rcar-gen4-hscif # R-Car Gen4 62 - const: renesas,hscif # generic HSCIF compatible UART 63 64 reg: 65 maxItems: 1 66 67 interrupts: 68 maxItems: 1 69 70 clocks: 71 minItems: 1 72 maxItems: 4 73 74 clock-names: 75 minItems: 1 76 maxItems: 4 77 items: 78 enum: 79 - fck # UART functional clock 80 - hsck # optional external clock input 81 - brg_int # optional internal clock source for BRG frequency divider 82 - scif_clk # optional external clock source for BRG frequency divider 83 84 power-domains: 85 maxItems: 1 86 87 resets: 88 maxItems: 1 89 90 dmas: 91 minItems: 2 92 maxItems: 4 93 description: 94 Must contain a list of pairs of references to DMA specifiers, one for 95 transmission, and one for reception. 96 97 dma-names: 98 minItems: 2 99 maxItems: 4 100 items: 101 enum: 102 - tx 103 - rx 104 105required: 106 - compatible 107 - reg 108 - interrupts 109 - clocks 110 - clock-names 111 - power-domains 112 113unevaluatedProperties: false 114 115if: 116 properties: 117 compatible: 118 contains: 119 enum: 120 - renesas,rcar-gen2-hscif 121 - renesas,rcar-gen3-hscif 122 - renesas,rcar-gen4-hscif 123then: 124 required: 125 - resets 126 127examples: 128 - | 129 #include <dt-bindings/clock/r8a7795-cpg-mssr.h> 130 #include <dt-bindings/interrupt-controller/arm-gic.h> 131 #include <dt-bindings/power/r8a7795-sysc.h> 132 aliases { 133 serial1 = &hscif1; 134 }; 135 136 hscif1: serial@e6550000 { 137 compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", 138 "renesas,hscif"; 139 reg = <0xe6550000 96>; 140 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&cpg CPG_MOD 519>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, 142 <&scif_clk>; 143 clock-names = "fck", "brg_int", "scif_clk"; 144 dmas = <&dmac1 0x33>, <&dmac1 0x32>, <&dmac2 0x33>, <&dmac2 0x32>; 145 dma-names = "tx", "rx", "tx", "rx"; 146 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 147 resets = <&cpg 519>; 148 uart-has-rtscts; 149 }; 150