1*19401e97SKuldeep Singh# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*19401e97SKuldeep Singh%YAML 1.2 3*19401e97SKuldeep Singh--- 4*19401e97SKuldeep Singh$id: "http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml#" 5*19401e97SKuldeep Singh$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*19401e97SKuldeep Singh 7*19401e97SKuldeep Singhtitle: Qualcomm Geni based QUP UART interface 8*19401e97SKuldeep Singh 9*19401e97SKuldeep Singhmaintainers: 10*19401e97SKuldeep Singh - Andy Gross <agross@kernel.org> 11*19401e97SKuldeep Singh - Bjorn Andersson <bjorn.andersson@linaro.org> 12*19401e97SKuldeep Singh 13*19401e97SKuldeep SinghallOf: 14*19401e97SKuldeep Singh - $ref: /schemas/serial/serial.yaml# 15*19401e97SKuldeep Singh 16*19401e97SKuldeep Singhproperties: 17*19401e97SKuldeep Singh compatible: 18*19401e97SKuldeep Singh enum: 19*19401e97SKuldeep Singh - qcom,geni-uart 20*19401e97SKuldeep Singh - qcom,geni-debug-uart 21*19401e97SKuldeep Singh 22*19401e97SKuldeep Singh clocks: 23*19401e97SKuldeep Singh maxItems: 1 24*19401e97SKuldeep Singh 25*19401e97SKuldeep Singh clock-names: 26*19401e97SKuldeep Singh const: se 27*19401e97SKuldeep Singh 28*19401e97SKuldeep Singh interconnects: 29*19401e97SKuldeep Singh maxItems: 2 30*19401e97SKuldeep Singh 31*19401e97SKuldeep Singh interconnect-names: 32*19401e97SKuldeep Singh items: 33*19401e97SKuldeep Singh - const: qup-core 34*19401e97SKuldeep Singh - const: qup-config 35*19401e97SKuldeep Singh 36*19401e97SKuldeep Singh interrupts: 37*19401e97SKuldeep Singh minItems: 1 38*19401e97SKuldeep Singh items: 39*19401e97SKuldeep Singh - description: UART core irq 40*19401e97SKuldeep Singh - description: Wakeup irq (RX GPIO) 41*19401e97SKuldeep Singh 42*19401e97SKuldeep Singh operating-points-v2: true 43*19401e97SKuldeep Singh 44*19401e97SKuldeep Singh pinctrl-0: true 45*19401e97SKuldeep Singh pinctrl-1: true 46*19401e97SKuldeep Singh 47*19401e97SKuldeep Singh pinctrl-names: 48*19401e97SKuldeep Singh minItems: 1 49*19401e97SKuldeep Singh items: 50*19401e97SKuldeep Singh - const: default 51*19401e97SKuldeep Singh - const: sleep 52*19401e97SKuldeep Singh 53*19401e97SKuldeep Singh power-domains: 54*19401e97SKuldeep Singh maxItems: 1 55*19401e97SKuldeep Singh 56*19401e97SKuldeep Singh reg: 57*19401e97SKuldeep Singh maxItems: 1 58*19401e97SKuldeep Singh 59*19401e97SKuldeep Singhrequired: 60*19401e97SKuldeep Singh - compatible 61*19401e97SKuldeep Singh - clocks 62*19401e97SKuldeep Singh - clock-names 63*19401e97SKuldeep Singh - interrupts 64*19401e97SKuldeep Singh - reg 65*19401e97SKuldeep Singh 66*19401e97SKuldeep SinghunevaluatedProperties: false 67*19401e97SKuldeep Singh 68*19401e97SKuldeep Singhexamples: 69*19401e97SKuldeep Singh - | 70*19401e97SKuldeep Singh #include <dt-bindings/interrupt-controller/arm-gic.h> 71*19401e97SKuldeep Singh #include <dt-bindings/clock/qcom,gcc-sc7180.h> 72*19401e97SKuldeep Singh #include <dt-bindings/interconnect/qcom,sc7180.h> 73*19401e97SKuldeep Singh 74*19401e97SKuldeep Singh serial@a88000 { 75*19401e97SKuldeep Singh compatible = "qcom,geni-uart"; 76*19401e97SKuldeep Singh reg = <0xa88000 0x7000>; 77*19401e97SKuldeep Singh interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 78*19401e97SKuldeep Singh clock-names = "se"; 79*19401e97SKuldeep Singh clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 80*19401e97SKuldeep Singh pinctrl-0 = <&qup_uart0_default>; 81*19401e97SKuldeep Singh pinctrl-names = "default"; 82*19401e97SKuldeep Singh interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 83*19401e97SKuldeep Singh <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 84*19401e97SKuldeep Singh interconnect-names = "qup-core", "qup-config"; 85*19401e97SKuldeep Singh }; 86*19401e97SKuldeep Singh... 87