119401e97SKuldeep Singh# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 219401e97SKuldeep Singh%YAML 1.2 319401e97SKuldeep Singh--- 4*cb95de8dSRob Herring$id: http://devicetree.org/schemas/serial/qcom,serial-geni-qcom.yaml# 5*cb95de8dSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 619401e97SKuldeep Singh 719401e97SKuldeep Singhtitle: Qualcomm Geni based QUP UART interface 819401e97SKuldeep Singh 919401e97SKuldeep Singhmaintainers: 1019401e97SKuldeep Singh - Andy Gross <agross@kernel.org> 1119401e97SKuldeep Singh - Bjorn Andersson <bjorn.andersson@linaro.org> 1219401e97SKuldeep Singh 1319401e97SKuldeep SinghallOf: 1419401e97SKuldeep Singh - $ref: /schemas/serial/serial.yaml# 1519401e97SKuldeep Singh 1619401e97SKuldeep Singhproperties: 1719401e97SKuldeep Singh compatible: 1819401e97SKuldeep Singh enum: 1919401e97SKuldeep Singh - qcom,geni-uart 2019401e97SKuldeep Singh - qcom,geni-debug-uart 2119401e97SKuldeep Singh 2219401e97SKuldeep Singh clocks: 2319401e97SKuldeep Singh maxItems: 1 2419401e97SKuldeep Singh 2519401e97SKuldeep Singh clock-names: 2619401e97SKuldeep Singh const: se 2719401e97SKuldeep Singh 2819401e97SKuldeep Singh interconnects: 2919401e97SKuldeep Singh maxItems: 2 3019401e97SKuldeep Singh 3119401e97SKuldeep Singh interconnect-names: 3219401e97SKuldeep Singh items: 3319401e97SKuldeep Singh - const: qup-core 3419401e97SKuldeep Singh - const: qup-config 3519401e97SKuldeep Singh 3619401e97SKuldeep Singh interrupts: 3719401e97SKuldeep Singh minItems: 1 3819401e97SKuldeep Singh items: 3919401e97SKuldeep Singh - description: UART core irq 4019401e97SKuldeep Singh - description: Wakeup irq (RX GPIO) 4119401e97SKuldeep Singh 4219401e97SKuldeep Singh operating-points-v2: true 4319401e97SKuldeep Singh 4419401e97SKuldeep Singh pinctrl-0: true 4519401e97SKuldeep Singh pinctrl-1: true 4619401e97SKuldeep Singh 4719401e97SKuldeep Singh pinctrl-names: 4819401e97SKuldeep Singh minItems: 1 4919401e97SKuldeep Singh items: 5019401e97SKuldeep Singh - const: default 5119401e97SKuldeep Singh - const: sleep 5219401e97SKuldeep Singh 5319401e97SKuldeep Singh power-domains: 5419401e97SKuldeep Singh maxItems: 1 5519401e97SKuldeep Singh 5619401e97SKuldeep Singh reg: 5719401e97SKuldeep Singh maxItems: 1 5819401e97SKuldeep Singh 5919401e97SKuldeep Singhrequired: 6019401e97SKuldeep Singh - compatible 6119401e97SKuldeep Singh - clocks 6219401e97SKuldeep Singh - clock-names 6319401e97SKuldeep Singh - interrupts 6419401e97SKuldeep Singh - reg 6519401e97SKuldeep Singh 6619401e97SKuldeep SinghunevaluatedProperties: false 6719401e97SKuldeep Singh 6819401e97SKuldeep Singhexamples: 6919401e97SKuldeep Singh - | 7019401e97SKuldeep Singh #include <dt-bindings/interrupt-controller/arm-gic.h> 7119401e97SKuldeep Singh #include <dt-bindings/clock/qcom,gcc-sc7180.h> 7219401e97SKuldeep Singh #include <dt-bindings/interconnect/qcom,sc7180.h> 7319401e97SKuldeep Singh 7419401e97SKuldeep Singh serial@a88000 { 7519401e97SKuldeep Singh compatible = "qcom,geni-uart"; 7619401e97SKuldeep Singh reg = <0xa88000 0x7000>; 7719401e97SKuldeep Singh interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 7819401e97SKuldeep Singh clock-names = "se"; 7919401e97SKuldeep Singh clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 8019401e97SKuldeep Singh pinctrl-0 = <&qup_uart0_default>; 8119401e97SKuldeep Singh pinctrl-names = "default"; 8219401e97SKuldeep Singh interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 8319401e97SKuldeep Singh <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 8419401e97SKuldeep Singh interconnect-names = "qup-core", "qup-config"; 8519401e97SKuldeep Singh }; 8619401e97SKuldeep Singh... 87