1# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/8250.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: UART (Universal Asynchronous Receiver/Transmitter) bindings
8
9maintainers:
10  - devicetree@vger.kernel.org
11
12allOf:
13  - $ref: serial.yaml#
14  - if:
15      anyOf:
16        - required:
17            - aspeed,lpc-io-reg
18        - required:
19            - aspeed,lpc-interrupts
20        - required:
21            - aspeed,sirq-polarity-sense
22    then:
23      properties:
24        compatible:
25          const: aspeed,ast2500-vuart
26  - if:
27      properties:
28        compatible:
29          const: mrvl,mmp-uart
30    then:
31      properties:
32        reg-shift:
33          const: 2
34      required:
35        - reg-shift
36  - if:
37      not:
38        properties:
39          compatible:
40            items:
41              - enum:
42                  - ns8250
43                  - ns16450
44                  - ns16550
45                  - ns16550a
46    then:
47      anyOf:
48        - required: [ clock-frequency ]
49        - required: [ clocks ]
50
51properties:
52  compatible:
53    oneOf:
54      - const: ns8250
55      - const: ns16450
56      - const: ns16550
57      - const: ns16550a
58      - const: ns16850
59      - const: aspeed,ast2400-vuart
60      - const: aspeed,ast2500-vuart
61      - const: intel,xscale-uart
62      - const: mrvl,pxa-uart
63      - const: nuvoton,wpcm450-uart
64      - const: nuvoton,npcm750-uart
65      - const: nvidia,tegra20-uart
66      - const: nxp,lpc3220-uart
67      - items:
68          - enum:
69              - altr,16550-FIFO32
70              - altr,16550-FIFO64
71              - altr,16550-FIFO128
72              - fsl,16550-FIFO64
73              - fsl,ns16550
74              - andestech,uart16550
75              - nxp,lpc1850-uart
76              - opencores,uart16550-rtlsvn105
77              - ti,da830-uart
78          - const: ns16550a
79      - items:
80          - enum:
81              - ns16750
82              - cavium,octeon-3860-uart
83              - xlnx,xps-uart16550-2.00.b
84              - ralink,rt2880-uart
85          - enum:
86              - ns16550 # Deprecated, unless the FIFO really is broken
87              - ns16550a
88      - items:
89          - enum:
90              - ralink,mt7620a-uart
91              - ralink,rt3052-uart
92              - ralink,rt3883-uart
93          - const: ralink,rt2880-uart
94          - enum:
95              - ns16550 # Deprecated, unless the FIFO really is broken
96              - ns16550a
97      - items:
98          - enum:
99              - mediatek,mt7622-btif
100              - mediatek,mt7623-btif
101          - const: mediatek,mtk-btif
102      - items:
103          - const: mrvl,mmp-uart
104          - const: intel,xscale-uart
105      - items:
106          - enum:
107              - nvidia,tegra30-uart
108              - nvidia,tegra114-uart
109              - nvidia,tegra124-uart
110              - nvidia,tegra186-uart
111              - nvidia,tegra194-uart
112              - nvidia,tegra210-uart
113          - const: nvidia,tegra20-uart
114
115  reg:
116    maxItems: 1
117
118  interrupts:
119    maxItems: 1
120
121  clock-frequency: true
122
123  clocks:
124    maxItems: 1
125
126  resets:
127    maxItems: 1
128
129  current-speed:
130    $ref: /schemas/types.yaml#/definitions/uint32
131    description: The current active speed of the UART.
132
133  reg-offset:
134    description: |
135      Offset to apply to the mapbase from the start of the registers.
136
137  reg-shift:
138    description: Quantity to shift the register offsets by.
139
140  reg-io-width:
141    description: |
142      The size (in bytes) of the IO accesses that should be performed on the
143      device. There are some systems that require 32-bit accesses to the
144      UART (e.g. TI davinci).
145
146  used-by-rtas:
147    type: boolean
148    description: |
149      Set to indicate that the port is in use by the OpenFirmware RTAS and
150      should not be registered.
151
152  no-loopback-test:
153    type: boolean
154    description: |
155      Set to indicate that the port does not implement loopback test mode.
156
157  fifo-size:
158    $ref: /schemas/types.yaml#/definitions/uint32
159    description: The fifo size of the UART.
160
161  auto-flow-control:
162    type: boolean
163    description: |
164      One way to enable automatic flow control support. The driver is
165      allowed to detect support for the capability even without this
166      property.
167
168  tx-threshold:
169    description: |
170      Specify the TX FIFO low water indication for parts with programmable
171      TX FIFO thresholds.
172
173  overrun-throttle-ms:
174    description: |
175      How long to pause uart rx when input overrun is encountered.
176
177  rts-gpios: true
178  cts-gpios: true
179  dtr-gpios: true
180  dsr-gpios: true
181  rng-gpios: true
182  dcd-gpios: true
183
184  aspeed,sirq-polarity-sense:
185    $ref: /schemas/types.yaml#/definitions/phandle-array
186    description: |
187      Phandle to aspeed,ast2500-scu compatible syscon alongside register
188      offset and bit number to identify how the SIRQ polarity should be
189      configured. One possible data source is the LPC/eSPI mode bit. Only
190      applicable to aspeed,ast2500-vuart.
191    deprecated: true
192
193  aspeed,lpc-io-reg:
194    $ref: '/schemas/types.yaml#/definitions/uint32'
195    description: |
196      The VUART LPC address.  Only applicable to aspeed,ast2500-vuart.
197
198  aspeed,lpc-interrupts:
199    $ref: "/schemas/types.yaml#/definitions/uint32-array"
200    minItems: 2
201    maxItems: 2
202    description: |
203      A 2-cell property describing the VUART SIRQ number and SIRQ
204      polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH).  Only
205      applicable to aspeed,ast2500-vuart.
206
207required:
208  - reg
209  - interrupts
210
211unevaluatedProperties: false
212
213examples:
214  - |
215    serial@80230000 {
216        compatible = "ns8250";
217        reg = <0x80230000 0x100>;
218        interrupts = <10>;
219        reg-shift = <2>;
220        clock-frequency = <48000000>;
221    };
222  - |
223    #include <dt-bindings/gpio/gpio.h>
224    serial@49042000 {
225        compatible = "andestech,uart16550", "ns16550a";
226        reg = <0x49042000 0x400>;
227        interrupts = <80>;
228        clock-frequency = <48000000>;
229        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
230        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
231        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
232        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
233        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
234        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
235    };
236  - |
237    #include <dt-bindings/clock/aspeed-clock.h>
238    #include <dt-bindings/interrupt-controller/irq.h>
239    serial@1e787000 {
240        compatible = "aspeed,ast2500-vuart";
241        reg = <0x1e787000 0x40>;
242        reg-shift = <2>;
243        interrupts = <8>;
244        clocks = <&syscon ASPEED_CLK_APB>;
245        no-loopback-test;
246        aspeed,lpc-io-reg = <0x3f8>;
247        aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
248    };
249
250...
251