1e69f5dc6SLubomir Rintel# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk> 2e69f5dc6SLubomir Rintel%YAML 1.2 3e69f5dc6SLubomir Rintel--- 4e69f5dc6SLubomir Rintel$id: http://devicetree.org/schemas/serial/8250.yaml# 5e69f5dc6SLubomir Rintel$schema: http://devicetree.org/meta-schemas/core.yaml# 6e69f5dc6SLubomir Rintel 7e69f5dc6SLubomir Rinteltitle: UART (Universal Asynchronous Receiver/Transmitter) bindings 8e69f5dc6SLubomir Rintel 9e69f5dc6SLubomir Rintelmaintainers: 10e69f5dc6SLubomir Rintel - devicetree@vger.kernel.org 11e69f5dc6SLubomir Rintel 12e69f5dc6SLubomir RintelallOf: 13*8f082dcfSZhen Lei - $ref: serial.yaml# 14e69f5dc6SLubomir Rintel - if: 15845766b6SZev Weiss anyOf: 16845766b6SZev Weiss - required: 17845766b6SZev Weiss - aspeed,lpc-io-reg 18845766b6SZev Weiss - required: 19845766b6SZev Weiss - aspeed,lpc-interrupts 20845766b6SZev Weiss - required: 21e69f5dc6SLubomir Rintel - aspeed,sirq-polarity-sense 22e69f5dc6SLubomir Rintel then: 23e69f5dc6SLubomir Rintel properties: 24e69f5dc6SLubomir Rintel compatible: 25e69f5dc6SLubomir Rintel const: aspeed,ast2500-vuart 26e69f5dc6SLubomir Rintel - if: 27e69f5dc6SLubomir Rintel properties: 28e69f5dc6SLubomir Rintel compatible: 29e69f5dc6SLubomir Rintel const: mrvl,mmp-uart 30e69f5dc6SLubomir Rintel then: 31e69f5dc6SLubomir Rintel properties: 32e69f5dc6SLubomir Rintel reg-shift: 33e69f5dc6SLubomir Rintel const: 2 34e69f5dc6SLubomir Rintel required: 35e69f5dc6SLubomir Rintel - reg-shift 36e69f5dc6SLubomir Rintel - if: 37e69f5dc6SLubomir Rintel not: 38e69f5dc6SLubomir Rintel properties: 39e69f5dc6SLubomir Rintel compatible: 40e69f5dc6SLubomir Rintel items: 41e69f5dc6SLubomir Rintel - enum: 42e69f5dc6SLubomir Rintel - ns8250 43e69f5dc6SLubomir Rintel - ns16450 44e69f5dc6SLubomir Rintel - ns16550 45e69f5dc6SLubomir Rintel - ns16550a 46e69f5dc6SLubomir Rintel then: 47e69f5dc6SLubomir Rintel anyOf: 48e69f5dc6SLubomir Rintel - required: [ clock-frequency ] 49e69f5dc6SLubomir Rintel - required: [ clocks ] 50e69f5dc6SLubomir Rintel 51e69f5dc6SLubomir Rintelproperties: 52e69f5dc6SLubomir Rintel compatible: 53e69f5dc6SLubomir Rintel oneOf: 54e69f5dc6SLubomir Rintel - const: ns8250 55e69f5dc6SLubomir Rintel - const: ns16450 56e69f5dc6SLubomir Rintel - const: ns16550 57e69f5dc6SLubomir Rintel - const: ns16550a 58e69f5dc6SLubomir Rintel - const: ns16850 59e69f5dc6SLubomir Rintel - const: aspeed,ast2400-vuart 60e69f5dc6SLubomir Rintel - const: aspeed,ast2500-vuart 61e69f5dc6SLubomir Rintel - const: intel,xscale-uart 62e69f5dc6SLubomir Rintel - const: mrvl,pxa-uart 633ece873eSJonathan Neuschäfer - const: nuvoton,wpcm450-uart 64e69f5dc6SLubomir Rintel - const: nuvoton,npcm750-uart 65e69f5dc6SLubomir Rintel - const: nvidia,tegra20-uart 66e69f5dc6SLubomir Rintel - const: nxp,lpc3220-uart 67e69f5dc6SLubomir Rintel - items: 68e69f5dc6SLubomir Rintel - enum: 69e69f5dc6SLubomir Rintel - altr,16550-FIFO32 70e69f5dc6SLubomir Rintel - altr,16550-FIFO64 71e69f5dc6SLubomir Rintel - altr,16550-FIFO128 72e69f5dc6SLubomir Rintel - fsl,16550-FIFO64 73e69f5dc6SLubomir Rintel - fsl,ns16550 74e69f5dc6SLubomir Rintel - andestech,uart16550 75e69f5dc6SLubomir Rintel - nxp,lpc1850-uart 76e69f5dc6SLubomir Rintel - opencores,uart16550-rtlsvn105 77e69f5dc6SLubomir Rintel - ti,da830-uart 78e69f5dc6SLubomir Rintel - const: ns16550a 79e69f5dc6SLubomir Rintel - items: 80e69f5dc6SLubomir Rintel - enum: 81e69f5dc6SLubomir Rintel - ns16750 82e69f5dc6SLubomir Rintel - cavium,octeon-3860-uart 83e69f5dc6SLubomir Rintel - xlnx,xps-uart16550-2.00.b 84e69f5dc6SLubomir Rintel - ralink,rt2880-uart 85e69f5dc6SLubomir Rintel - enum: 86e69f5dc6SLubomir Rintel - ns16550 # Deprecated, unless the FIFO really is broken 87e69f5dc6SLubomir Rintel - ns16550a 88e69f5dc6SLubomir Rintel - items: 89e69f5dc6SLubomir Rintel - enum: 90e69f5dc6SLubomir Rintel - ralink,mt7620a-uart 91e69f5dc6SLubomir Rintel - ralink,rt3052-uart 92e69f5dc6SLubomir Rintel - ralink,rt3883-uart 93e69f5dc6SLubomir Rintel - const: ralink,rt2880-uart 94e69f5dc6SLubomir Rintel - enum: 95e69f5dc6SLubomir Rintel - ns16550 # Deprecated, unless the FIFO really is broken 96e69f5dc6SLubomir Rintel - ns16550a 97e69f5dc6SLubomir Rintel - items: 98e69f5dc6SLubomir Rintel - enum: 99e69f5dc6SLubomir Rintel - mediatek,mt7622-btif 100e69f5dc6SLubomir Rintel - mediatek,mt7623-btif 101e69f5dc6SLubomir Rintel - const: mediatek,mtk-btif 102e69f5dc6SLubomir Rintel - items: 103e69f5dc6SLubomir Rintel - const: mrvl,mmp-uart 104e69f5dc6SLubomir Rintel - const: intel,xscale-uart 105e69f5dc6SLubomir Rintel - items: 106e69f5dc6SLubomir Rintel - enum: 107e69f5dc6SLubomir Rintel - nvidia,tegra30-uart 108e69f5dc6SLubomir Rintel - nvidia,tegra114-uart 109e69f5dc6SLubomir Rintel - nvidia,tegra124-uart 110e69f5dc6SLubomir Rintel - nvidia,tegra186-uart 111e69f5dc6SLubomir Rintel - nvidia,tegra194-uart 112e69f5dc6SLubomir Rintel - nvidia,tegra210-uart 113e69f5dc6SLubomir Rintel - const: nvidia,tegra20-uart 114e69f5dc6SLubomir Rintel 115e69f5dc6SLubomir Rintel reg: 116e69f5dc6SLubomir Rintel maxItems: 1 117e69f5dc6SLubomir Rintel 118e69f5dc6SLubomir Rintel interrupts: 119e69f5dc6SLubomir Rintel maxItems: 1 120e69f5dc6SLubomir Rintel 121e69f5dc6SLubomir Rintel clock-frequency: true 122e69f5dc6SLubomir Rintel 123e69f5dc6SLubomir Rintel clocks: 124e69f5dc6SLubomir Rintel maxItems: 1 125e69f5dc6SLubomir Rintel 126e69f5dc6SLubomir Rintel resets: 127e69f5dc6SLubomir Rintel maxItems: 1 128e69f5dc6SLubomir Rintel 129e69f5dc6SLubomir Rintel current-speed: 130d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 131e69f5dc6SLubomir Rintel description: The current active speed of the UART. 132e69f5dc6SLubomir Rintel 133e69f5dc6SLubomir Rintel reg-offset: 134e69f5dc6SLubomir Rintel description: | 135e69f5dc6SLubomir Rintel Offset to apply to the mapbase from the start of the registers. 136e69f5dc6SLubomir Rintel 137e69f5dc6SLubomir Rintel reg-shift: 138e69f5dc6SLubomir Rintel description: Quantity to shift the register offsets by. 139e69f5dc6SLubomir Rintel 140e69f5dc6SLubomir Rintel reg-io-width: 141e69f5dc6SLubomir Rintel description: | 142e69f5dc6SLubomir Rintel The size (in bytes) of the IO accesses that should be performed on the 143e69f5dc6SLubomir Rintel device. There are some systems that require 32-bit accesses to the 144e69f5dc6SLubomir Rintel UART (e.g. TI davinci). 145e69f5dc6SLubomir Rintel 146e69f5dc6SLubomir Rintel used-by-rtas: 147e69f5dc6SLubomir Rintel type: boolean 148e69f5dc6SLubomir Rintel description: | 149e69f5dc6SLubomir Rintel Set to indicate that the port is in use by the OpenFirmware RTAS and 150e69f5dc6SLubomir Rintel should not be registered. 151e69f5dc6SLubomir Rintel 152e69f5dc6SLubomir Rintel no-loopback-test: 153e69f5dc6SLubomir Rintel type: boolean 154e69f5dc6SLubomir Rintel description: | 155e69f5dc6SLubomir Rintel Set to indicate that the port does not implement loopback test mode. 156e69f5dc6SLubomir Rintel 157e69f5dc6SLubomir Rintel fifo-size: 158d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 159e69f5dc6SLubomir Rintel description: The fifo size of the UART. 160e69f5dc6SLubomir Rintel 161e69f5dc6SLubomir Rintel auto-flow-control: 162e69f5dc6SLubomir Rintel type: boolean 163e69f5dc6SLubomir Rintel description: | 164e69f5dc6SLubomir Rintel One way to enable automatic flow control support. The driver is 165e69f5dc6SLubomir Rintel allowed to detect support for the capability even without this 166e69f5dc6SLubomir Rintel property. 167e69f5dc6SLubomir Rintel 168e69f5dc6SLubomir Rintel tx-threshold: 169e69f5dc6SLubomir Rintel description: | 170e69f5dc6SLubomir Rintel Specify the TX FIFO low water indication for parts with programmable 171e69f5dc6SLubomir Rintel TX FIFO thresholds. 172e69f5dc6SLubomir Rintel 173e69f5dc6SLubomir Rintel overrun-throttle-ms: 174e69f5dc6SLubomir Rintel description: | 175e69f5dc6SLubomir Rintel How long to pause uart rx when input overrun is encountered. 176e69f5dc6SLubomir Rintel 177e69f5dc6SLubomir Rintel rts-gpios: true 178e69f5dc6SLubomir Rintel cts-gpios: true 179e69f5dc6SLubomir Rintel dtr-gpios: true 180e69f5dc6SLubomir Rintel dsr-gpios: true 181e69f5dc6SLubomir Rintel rng-gpios: true 182e69f5dc6SLubomir Rintel dcd-gpios: true 183e69f5dc6SLubomir Rintel 184e69f5dc6SLubomir Rintel aspeed,sirq-polarity-sense: 185e69f5dc6SLubomir Rintel $ref: /schemas/types.yaml#/definitions/phandle-array 186e69f5dc6SLubomir Rintel description: | 187e69f5dc6SLubomir Rintel Phandle to aspeed,ast2500-scu compatible syscon alongside register 188e69f5dc6SLubomir Rintel offset and bit number to identify how the SIRQ polarity should be 189e69f5dc6SLubomir Rintel configured. One possible data source is the LPC/eSPI mode bit. Only 190e69f5dc6SLubomir Rintel applicable to aspeed,ast2500-vuart. 191a13df3beSZev Weiss deprecated: true 192e69f5dc6SLubomir Rintel 193845766b6SZev Weiss aspeed,lpc-io-reg: 194845766b6SZev Weiss $ref: '/schemas/types.yaml#/definitions/uint32' 195845766b6SZev Weiss description: | 196845766b6SZev Weiss The VUART LPC address. Only applicable to aspeed,ast2500-vuart. 197845766b6SZev Weiss 198845766b6SZev Weiss aspeed,lpc-interrupts: 199845766b6SZev Weiss $ref: "/schemas/types.yaml#/definitions/uint32-array" 200845766b6SZev Weiss minItems: 2 201845766b6SZev Weiss maxItems: 2 202845766b6SZev Weiss description: | 203845766b6SZev Weiss A 2-cell property describing the VUART SIRQ number and SIRQ 204845766b6SZev Weiss polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only 205845766b6SZev Weiss applicable to aspeed,ast2500-vuart. 206845766b6SZev Weiss 207e69f5dc6SLubomir Rintelrequired: 208e69f5dc6SLubomir Rintel - reg 209e69f5dc6SLubomir Rintel - interrupts 210e69f5dc6SLubomir Rintel 211e69f5dc6SLubomir RintelunevaluatedProperties: false 212e69f5dc6SLubomir Rintel 213e69f5dc6SLubomir Rintelexamples: 214e69f5dc6SLubomir Rintel - | 215e69f5dc6SLubomir Rintel serial@80230000 { 216e69f5dc6SLubomir Rintel compatible = "ns8250"; 217e69f5dc6SLubomir Rintel reg = <0x80230000 0x100>; 218e69f5dc6SLubomir Rintel interrupts = <10>; 219e69f5dc6SLubomir Rintel reg-shift = <2>; 220e69f5dc6SLubomir Rintel clock-frequency = <48000000>; 221e69f5dc6SLubomir Rintel }; 222e69f5dc6SLubomir Rintel - | 223e69f5dc6SLubomir Rintel #include <dt-bindings/gpio/gpio.h> 224e69f5dc6SLubomir Rintel serial@49042000 { 225e69f5dc6SLubomir Rintel compatible = "andestech,uart16550", "ns16550a"; 226e69f5dc6SLubomir Rintel reg = <0x49042000 0x400>; 227e69f5dc6SLubomir Rintel interrupts = <80>; 228e69f5dc6SLubomir Rintel clock-frequency = <48000000>; 229e69f5dc6SLubomir Rintel cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 230e69f5dc6SLubomir Rintel rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 231e69f5dc6SLubomir Rintel dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 232e69f5dc6SLubomir Rintel dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 233e69f5dc6SLubomir Rintel dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 234e69f5dc6SLubomir Rintel rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 235e69f5dc6SLubomir Rintel }; 236e69f5dc6SLubomir Rintel - | 237e69f5dc6SLubomir Rintel #include <dt-bindings/clock/aspeed-clock.h> 238845766b6SZev Weiss #include <dt-bindings/interrupt-controller/irq.h> 239e69f5dc6SLubomir Rintel serial@1e787000 { 240e69f5dc6SLubomir Rintel compatible = "aspeed,ast2500-vuart"; 241e69f5dc6SLubomir Rintel reg = <0x1e787000 0x40>; 242e69f5dc6SLubomir Rintel reg-shift = <2>; 243e69f5dc6SLubomir Rintel interrupts = <8>; 244e69f5dc6SLubomir Rintel clocks = <&syscon ASPEED_CLK_APB>; 245e69f5dc6SLubomir Rintel no-loopback-test; 246845766b6SZev Weiss aspeed,lpc-io-reg = <0x3f8>; 247845766b6SZev Weiss aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 248e69f5dc6SLubomir Rintel }; 249e69f5dc6SLubomir Rintel 250e69f5dc6SLubomir Rintel... 251