1e69f5dc6SLubomir Rintel# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk> 2e69f5dc6SLubomir Rintel%YAML 1.2 3e69f5dc6SLubomir Rintel--- 4e69f5dc6SLubomir Rintel$id: http://devicetree.org/schemas/serial/8250.yaml# 5e69f5dc6SLubomir Rintel$schema: http://devicetree.org/meta-schemas/core.yaml# 6e69f5dc6SLubomir Rintel 7*84e85359SKrzysztof Kozlowskititle: UART (Universal Asynchronous Receiver/Transmitter) 8e69f5dc6SLubomir Rintel 9e69f5dc6SLubomir Rintelmaintainers: 10e69f5dc6SLubomir Rintel - devicetree@vger.kernel.org 11e69f5dc6SLubomir Rintel 12e69f5dc6SLubomir RintelallOf: 138f082dcfSZhen Lei - $ref: serial.yaml# 14e69f5dc6SLubomir Rintel - if: 15845766b6SZev Weiss anyOf: 16845766b6SZev Weiss - required: 17845766b6SZev Weiss - aspeed,lpc-io-reg 18845766b6SZev Weiss - required: 19845766b6SZev Weiss - aspeed,lpc-interrupts 20845766b6SZev Weiss - required: 21e69f5dc6SLubomir Rintel - aspeed,sirq-polarity-sense 22e69f5dc6SLubomir Rintel then: 23e69f5dc6SLubomir Rintel properties: 24e69f5dc6SLubomir Rintel compatible: 25e69f5dc6SLubomir Rintel const: aspeed,ast2500-vuart 26e69f5dc6SLubomir Rintel - if: 27e69f5dc6SLubomir Rintel properties: 28e69f5dc6SLubomir Rintel compatible: 29e69f5dc6SLubomir Rintel const: mrvl,mmp-uart 30e69f5dc6SLubomir Rintel then: 31e69f5dc6SLubomir Rintel properties: 32e69f5dc6SLubomir Rintel reg-shift: 33e69f5dc6SLubomir Rintel const: 2 34e69f5dc6SLubomir Rintel required: 35e69f5dc6SLubomir Rintel - reg-shift 36e69f5dc6SLubomir Rintel - if: 37e69f5dc6SLubomir Rintel not: 38e69f5dc6SLubomir Rintel properties: 39e69f5dc6SLubomir Rintel compatible: 40e69f5dc6SLubomir Rintel items: 41e69f5dc6SLubomir Rintel - enum: 42e69f5dc6SLubomir Rintel - ns8250 43e69f5dc6SLubomir Rintel - ns16450 44e69f5dc6SLubomir Rintel - ns16550 45e69f5dc6SLubomir Rintel - ns16550a 46e69f5dc6SLubomir Rintel then: 47e69f5dc6SLubomir Rintel anyOf: 48e69f5dc6SLubomir Rintel - required: [ clock-frequency ] 49e69f5dc6SLubomir Rintel - required: [ clocks ] 50e69f5dc6SLubomir Rintel 51e69f5dc6SLubomir Rintelproperties: 52e69f5dc6SLubomir Rintel compatible: 53e69f5dc6SLubomir Rintel oneOf: 54e69f5dc6SLubomir Rintel - const: ns8250 55e69f5dc6SLubomir Rintel - const: ns16450 56e69f5dc6SLubomir Rintel - const: ns16550 57e69f5dc6SLubomir Rintel - const: ns16550a 58e69f5dc6SLubomir Rintel - const: ns16850 59e69f5dc6SLubomir Rintel - const: aspeed,ast2400-vuart 60e69f5dc6SLubomir Rintel - const: aspeed,ast2500-vuart 61e69f5dc6SLubomir Rintel - const: intel,xscale-uart 62e69f5dc6SLubomir Rintel - const: mrvl,pxa-uart 633ece873eSJonathan Neuschäfer - const: nuvoton,wpcm450-uart 64e69f5dc6SLubomir Rintel - const: nuvoton,npcm750-uart 65c8177f90STomer Maimon - const: nuvoton,npcm845-uart 66e69f5dc6SLubomir Rintel - const: nvidia,tegra20-uart 67e69f5dc6SLubomir Rintel - const: nxp,lpc3220-uart 68e69f5dc6SLubomir Rintel - items: 69e69f5dc6SLubomir Rintel - enum: 70f444f34bSLinus Walleij - exar,xr16l2552 71f444f34bSLinus Walleij - exar,xr16l2551 72f444f34bSLinus Walleij - exar,xr16l2550 73f444f34bSLinus Walleij - const: ns8250 74f444f34bSLinus Walleij - items: 75f444f34bSLinus Walleij - enum: 76e69f5dc6SLubomir Rintel - altr,16550-FIFO32 77e69f5dc6SLubomir Rintel - altr,16550-FIFO64 78e69f5dc6SLubomir Rintel - altr,16550-FIFO128 79e69f5dc6SLubomir Rintel - fsl,16550-FIFO64 80e69f5dc6SLubomir Rintel - fsl,ns16550 81e69f5dc6SLubomir Rintel - andestech,uart16550 82e69f5dc6SLubomir Rintel - nxp,lpc1850-uart 83e69f5dc6SLubomir Rintel - opencores,uart16550-rtlsvn105 84e69f5dc6SLubomir Rintel - ti,da830-uart 85e69f5dc6SLubomir Rintel - const: ns16550a 86e69f5dc6SLubomir Rintel - items: 87e69f5dc6SLubomir Rintel - enum: 88e69f5dc6SLubomir Rintel - ns16750 89e69f5dc6SLubomir Rintel - cavium,octeon-3860-uart 90e69f5dc6SLubomir Rintel - xlnx,xps-uart16550-2.00.b 91e69f5dc6SLubomir Rintel - ralink,rt2880-uart 92e69f5dc6SLubomir Rintel - enum: 93e69f5dc6SLubomir Rintel - ns16550 # Deprecated, unless the FIFO really is broken 94e69f5dc6SLubomir Rintel - ns16550a 95e69f5dc6SLubomir Rintel - items: 96e69f5dc6SLubomir Rintel - enum: 97e69f5dc6SLubomir Rintel - ralink,mt7620a-uart 98e69f5dc6SLubomir Rintel - ralink,rt3052-uart 99e69f5dc6SLubomir Rintel - ralink,rt3883-uart 100e69f5dc6SLubomir Rintel - const: ralink,rt2880-uart 101e69f5dc6SLubomir Rintel - enum: 102e69f5dc6SLubomir Rintel - ns16550 # Deprecated, unless the FIFO really is broken 103e69f5dc6SLubomir Rintel - ns16550a 104e69f5dc6SLubomir Rintel - items: 105e69f5dc6SLubomir Rintel - enum: 106e69f5dc6SLubomir Rintel - mediatek,mt7622-btif 107e69f5dc6SLubomir Rintel - mediatek,mt7623-btif 108e69f5dc6SLubomir Rintel - const: mediatek,mtk-btif 109e69f5dc6SLubomir Rintel - items: 110e69f5dc6SLubomir Rintel - const: mrvl,mmp-uart 111e69f5dc6SLubomir Rintel - const: intel,xscale-uart 112e69f5dc6SLubomir Rintel - items: 113e69f5dc6SLubomir Rintel - enum: 114e69f5dc6SLubomir Rintel - nvidia,tegra30-uart 115e69f5dc6SLubomir Rintel - nvidia,tegra114-uart 116e69f5dc6SLubomir Rintel - nvidia,tegra124-uart 11796b594d2SThierry Reding - nvidia,tegra210-uart 118e69f5dc6SLubomir Rintel - nvidia,tegra186-uart 119e69f5dc6SLubomir Rintel - nvidia,tegra194-uart 12096b594d2SThierry Reding - nvidia,tegra234-uart 121e69f5dc6SLubomir Rintel - const: nvidia,tegra20-uart 122e69f5dc6SLubomir Rintel 123e69f5dc6SLubomir Rintel reg: 124e69f5dc6SLubomir Rintel maxItems: 1 125e69f5dc6SLubomir Rintel 126e69f5dc6SLubomir Rintel interrupts: 127e69f5dc6SLubomir Rintel maxItems: 1 128e69f5dc6SLubomir Rintel 129e69f5dc6SLubomir Rintel clock-frequency: true 130e69f5dc6SLubomir Rintel 131e69f5dc6SLubomir Rintel clocks: 132e69f5dc6SLubomir Rintel maxItems: 1 133e69f5dc6SLubomir Rintel 134e69f5dc6SLubomir Rintel resets: 135e69f5dc6SLubomir Rintel maxItems: 1 136e69f5dc6SLubomir Rintel 137e69f5dc6SLubomir Rintel current-speed: 138d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 139e69f5dc6SLubomir Rintel description: The current active speed of the UART. 140e69f5dc6SLubomir Rintel 141e69f5dc6SLubomir Rintel reg-offset: 1424e71ed98SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 143e69f5dc6SLubomir Rintel description: | 144e69f5dc6SLubomir Rintel Offset to apply to the mapbase from the start of the registers. 145e69f5dc6SLubomir Rintel 146e69f5dc6SLubomir Rintel reg-shift: 147e69f5dc6SLubomir Rintel description: Quantity to shift the register offsets by. 148e69f5dc6SLubomir Rintel 149e69f5dc6SLubomir Rintel reg-io-width: 150e69f5dc6SLubomir Rintel description: | 151e69f5dc6SLubomir Rintel The size (in bytes) of the IO accesses that should be performed on the 152e69f5dc6SLubomir Rintel device. There are some systems that require 32-bit accesses to the 153e69f5dc6SLubomir Rintel UART (e.g. TI davinci). 154e69f5dc6SLubomir Rintel 155e69f5dc6SLubomir Rintel used-by-rtas: 156e69f5dc6SLubomir Rintel type: boolean 157e69f5dc6SLubomir Rintel description: | 158e69f5dc6SLubomir Rintel Set to indicate that the port is in use by the OpenFirmware RTAS and 159e69f5dc6SLubomir Rintel should not be registered. 160e69f5dc6SLubomir Rintel 161e69f5dc6SLubomir Rintel no-loopback-test: 162e69f5dc6SLubomir Rintel type: boolean 163e69f5dc6SLubomir Rintel description: | 164e69f5dc6SLubomir Rintel Set to indicate that the port does not implement loopback test mode. 165e69f5dc6SLubomir Rintel 166e69f5dc6SLubomir Rintel fifo-size: 167d69c6dddSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 168e69f5dc6SLubomir Rintel description: The fifo size of the UART. 169e69f5dc6SLubomir Rintel 170e69f5dc6SLubomir Rintel auto-flow-control: 171e69f5dc6SLubomir Rintel type: boolean 172e69f5dc6SLubomir Rintel description: | 173e69f5dc6SLubomir Rintel One way to enable automatic flow control support. The driver is 174e69f5dc6SLubomir Rintel allowed to detect support for the capability even without this 175e69f5dc6SLubomir Rintel property. 176e69f5dc6SLubomir Rintel 177e69f5dc6SLubomir Rintel tx-threshold: 178e69f5dc6SLubomir Rintel description: | 179e69f5dc6SLubomir Rintel Specify the TX FIFO low water indication for parts with programmable 180e69f5dc6SLubomir Rintel TX FIFO thresholds. 181e69f5dc6SLubomir Rintel 182e69f5dc6SLubomir Rintel overrun-throttle-ms: 183e69f5dc6SLubomir Rintel description: | 184e69f5dc6SLubomir Rintel How long to pause uart rx when input overrun is encountered. 185e69f5dc6SLubomir Rintel 186e69f5dc6SLubomir Rintel rts-gpios: true 187e69f5dc6SLubomir Rintel cts-gpios: true 188e69f5dc6SLubomir Rintel dtr-gpios: true 189e69f5dc6SLubomir Rintel dsr-gpios: true 190e69f5dc6SLubomir Rintel rng-gpios: true 191e69f5dc6SLubomir Rintel dcd-gpios: true 192e69f5dc6SLubomir Rintel 193e69f5dc6SLubomir Rintel aspeed,sirq-polarity-sense: 194e69f5dc6SLubomir Rintel $ref: /schemas/types.yaml#/definitions/phandle-array 195e69f5dc6SLubomir Rintel description: | 196e69f5dc6SLubomir Rintel Phandle to aspeed,ast2500-scu compatible syscon alongside register 197e69f5dc6SLubomir Rintel offset and bit number to identify how the SIRQ polarity should be 198e69f5dc6SLubomir Rintel configured. One possible data source is the LPC/eSPI mode bit. Only 199e69f5dc6SLubomir Rintel applicable to aspeed,ast2500-vuart. 200a13df3beSZev Weiss deprecated: true 201e69f5dc6SLubomir Rintel 202845766b6SZev Weiss aspeed,lpc-io-reg: 203845766b6SZev Weiss $ref: '/schemas/types.yaml#/definitions/uint32' 204845766b6SZev Weiss description: | 205845766b6SZev Weiss The VUART LPC address. Only applicable to aspeed,ast2500-vuart. 206845766b6SZev Weiss 207845766b6SZev Weiss aspeed,lpc-interrupts: 208845766b6SZev Weiss $ref: "/schemas/types.yaml#/definitions/uint32-array" 209845766b6SZev Weiss minItems: 2 210845766b6SZev Weiss maxItems: 2 211845766b6SZev Weiss description: | 212845766b6SZev Weiss A 2-cell property describing the VUART SIRQ number and SIRQ 213845766b6SZev Weiss polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only 214845766b6SZev Weiss applicable to aspeed,ast2500-vuart. 215845766b6SZev Weiss 216e69f5dc6SLubomir Rintelrequired: 217e69f5dc6SLubomir Rintel - reg 218e69f5dc6SLubomir Rintel - interrupts 219e69f5dc6SLubomir Rintel 220e69f5dc6SLubomir RintelunevaluatedProperties: false 221e69f5dc6SLubomir Rintel 222e69f5dc6SLubomir Rintelexamples: 223e69f5dc6SLubomir Rintel - | 224e69f5dc6SLubomir Rintel serial@80230000 { 225e69f5dc6SLubomir Rintel compatible = "ns8250"; 226e69f5dc6SLubomir Rintel reg = <0x80230000 0x100>; 227e69f5dc6SLubomir Rintel interrupts = <10>; 228e69f5dc6SLubomir Rintel reg-shift = <2>; 229e69f5dc6SLubomir Rintel clock-frequency = <48000000>; 230e69f5dc6SLubomir Rintel }; 231e69f5dc6SLubomir Rintel - | 232e69f5dc6SLubomir Rintel #include <dt-bindings/gpio/gpio.h> 233e69f5dc6SLubomir Rintel serial@49042000 { 234e69f5dc6SLubomir Rintel compatible = "andestech,uart16550", "ns16550a"; 235e69f5dc6SLubomir Rintel reg = <0x49042000 0x400>; 236e69f5dc6SLubomir Rintel interrupts = <80>; 237e69f5dc6SLubomir Rintel clock-frequency = <48000000>; 238e69f5dc6SLubomir Rintel cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; 239e69f5dc6SLubomir Rintel rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; 240e69f5dc6SLubomir Rintel dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 241e69f5dc6SLubomir Rintel dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 242e69f5dc6SLubomir Rintel dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 243e69f5dc6SLubomir Rintel rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 244e69f5dc6SLubomir Rintel }; 245e69f5dc6SLubomir Rintel - | 246e69f5dc6SLubomir Rintel #include <dt-bindings/clock/aspeed-clock.h> 247845766b6SZev Weiss #include <dt-bindings/interrupt-controller/irq.h> 248e69f5dc6SLubomir Rintel serial@1e787000 { 249e69f5dc6SLubomir Rintel compatible = "aspeed,ast2500-vuart"; 250e69f5dc6SLubomir Rintel reg = <0x1e787000 0x40>; 251e69f5dc6SLubomir Rintel reg-shift = <2>; 252e69f5dc6SLubomir Rintel interrupts = <8>; 253e69f5dc6SLubomir Rintel clocks = <&syscon ASPEED_CLK_APB>; 254e69f5dc6SLubomir Rintel no-loopback-test; 255845766b6SZev Weiss aspeed,lpc-io-reg = <0x3f8>; 256845766b6SZev Weiss aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 257e69f5dc6SLubomir Rintel }; 258e69f5dc6SLubomir Rintel 259e69f5dc6SLubomir Rintel... 260