1e69f5dc6SLubomir Rintel# Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
2e69f5dc6SLubomir Rintel%YAML 1.2
3e69f5dc6SLubomir Rintel---
4e69f5dc6SLubomir Rintel$id: http://devicetree.org/schemas/serial/8250.yaml#
5e69f5dc6SLubomir Rintel$schema: http://devicetree.org/meta-schemas/core.yaml#
6e69f5dc6SLubomir Rintel
7e69f5dc6SLubomir Rinteltitle: UART (Universal Asynchronous Receiver/Transmitter) bindings
8e69f5dc6SLubomir Rintel
9e69f5dc6SLubomir Rintelmaintainers:
10e69f5dc6SLubomir Rintel  - devicetree@vger.kernel.org
11e69f5dc6SLubomir Rintel
12e69f5dc6SLubomir RintelallOf:
13e69f5dc6SLubomir Rintel  - $ref: /schemas/serial.yaml#
14e69f5dc6SLubomir Rintel  - if:
15e69f5dc6SLubomir Rintel      required:
16e69f5dc6SLubomir Rintel        - aspeed,sirq-polarity-sense
17e69f5dc6SLubomir Rintel    then:
18e69f5dc6SLubomir Rintel      properties:
19e69f5dc6SLubomir Rintel        compatible:
20e69f5dc6SLubomir Rintel          const: aspeed,ast2500-vuart
21e69f5dc6SLubomir Rintel  - if:
22e69f5dc6SLubomir Rintel      properties:
23e69f5dc6SLubomir Rintel        compatible:
24e69f5dc6SLubomir Rintel          const: mrvl,mmp-uart
25e69f5dc6SLubomir Rintel    then:
26e69f5dc6SLubomir Rintel      properties:
27e69f5dc6SLubomir Rintel        reg-shift:
28e69f5dc6SLubomir Rintel          const: 2
29e69f5dc6SLubomir Rintel      required:
30e69f5dc6SLubomir Rintel        - reg-shift
31e69f5dc6SLubomir Rintel  - if:
32e69f5dc6SLubomir Rintel      not:
33e69f5dc6SLubomir Rintel        properties:
34e69f5dc6SLubomir Rintel          compatible:
35e69f5dc6SLubomir Rintel            items:
36e69f5dc6SLubomir Rintel              - enum:
37e69f5dc6SLubomir Rintel                  - ns8250
38e69f5dc6SLubomir Rintel                  - ns16450
39e69f5dc6SLubomir Rintel                  - ns16550
40e69f5dc6SLubomir Rintel                  - ns16550a
41e69f5dc6SLubomir Rintel    then:
42e69f5dc6SLubomir Rintel      anyOf:
43e69f5dc6SLubomir Rintel        - required: [ clock-frequency ]
44e69f5dc6SLubomir Rintel        - required: [ clocks ]
45e69f5dc6SLubomir Rintel
46e69f5dc6SLubomir Rintelproperties:
47e69f5dc6SLubomir Rintel  compatible:
48e69f5dc6SLubomir Rintel    oneOf:
49e69f5dc6SLubomir Rintel      - const: ns8250
50e69f5dc6SLubomir Rintel      - const: ns16450
51e69f5dc6SLubomir Rintel      - const: ns16550
52e69f5dc6SLubomir Rintel      - const: ns16550a
53e69f5dc6SLubomir Rintel      - const: ns16850
54e69f5dc6SLubomir Rintel      - const: aspeed,ast2400-vuart
55e69f5dc6SLubomir Rintel      - const: aspeed,ast2500-vuart
56e69f5dc6SLubomir Rintel      - const: intel,xscale-uart
57e69f5dc6SLubomir Rintel      - const: mrvl,pxa-uart
58*3ece873eSJonathan Neuschäfer      - const: nuvoton,wpcm450-uart
59e69f5dc6SLubomir Rintel      - const: nuvoton,npcm750-uart
60e69f5dc6SLubomir Rintel      - const: nvidia,tegra20-uart
61e69f5dc6SLubomir Rintel      - const: nxp,lpc3220-uart
62e69f5dc6SLubomir Rintel      - items:
63e69f5dc6SLubomir Rintel          - enum:
64e69f5dc6SLubomir Rintel              - altr,16550-FIFO32
65e69f5dc6SLubomir Rintel              - altr,16550-FIFO64
66e69f5dc6SLubomir Rintel              - altr,16550-FIFO128
67e69f5dc6SLubomir Rintel              - fsl,16550-FIFO64
68e69f5dc6SLubomir Rintel              - fsl,ns16550
69e69f5dc6SLubomir Rintel              - andestech,uart16550
70e69f5dc6SLubomir Rintel              - nxp,lpc1850-uart
71e69f5dc6SLubomir Rintel              - opencores,uart16550-rtlsvn105
72e69f5dc6SLubomir Rintel              - ti,da830-uart
73e69f5dc6SLubomir Rintel          - const: ns16550a
74e69f5dc6SLubomir Rintel      - items:
75e69f5dc6SLubomir Rintel          - enum:
76e69f5dc6SLubomir Rintel              - ns16750
77e69f5dc6SLubomir Rintel              - cavium,octeon-3860-uart
78e69f5dc6SLubomir Rintel              - xlnx,xps-uart16550-2.00.b
79e69f5dc6SLubomir Rintel              - ralink,rt2880-uart
80e69f5dc6SLubomir Rintel          - enum:
81e69f5dc6SLubomir Rintel              - ns16550 # Deprecated, unless the FIFO really is broken
82e69f5dc6SLubomir Rintel              - ns16550a
83e69f5dc6SLubomir Rintel      - items:
84e69f5dc6SLubomir Rintel          - enum:
85e69f5dc6SLubomir Rintel              - ralink,mt7620a-uart
86e69f5dc6SLubomir Rintel              - ralink,rt3052-uart
87e69f5dc6SLubomir Rintel              - ralink,rt3883-uart
88e69f5dc6SLubomir Rintel          - const: ralink,rt2880-uart
89e69f5dc6SLubomir Rintel          - enum:
90e69f5dc6SLubomir Rintel              - ns16550 # Deprecated, unless the FIFO really is broken
91e69f5dc6SLubomir Rintel              - ns16550a
92e69f5dc6SLubomir Rintel      - items:
93e69f5dc6SLubomir Rintel          - enum:
94e69f5dc6SLubomir Rintel              - mediatek,mt7622-btif
95e69f5dc6SLubomir Rintel              - mediatek,mt7623-btif
96e69f5dc6SLubomir Rintel          - const: mediatek,mtk-btif
97e69f5dc6SLubomir Rintel      - items:
98e69f5dc6SLubomir Rintel          - enum:
99e69f5dc6SLubomir Rintel              - mediatek,mt7622-btif
100e69f5dc6SLubomir Rintel              - mediatek,mt7623-btif
101e69f5dc6SLubomir Rintel          - const: mediatek,mtk-btif
102e69f5dc6SLubomir Rintel      - items:
103e69f5dc6SLubomir Rintel          - const: mrvl,mmp-uart
104e69f5dc6SLubomir Rintel          - const: intel,xscale-uart
105e69f5dc6SLubomir Rintel      - items:
106e69f5dc6SLubomir Rintel          - enum:
107e69f5dc6SLubomir Rintel              - nvidia,tegra30-uart
108e69f5dc6SLubomir Rintel              - nvidia,tegra114-uart
109e69f5dc6SLubomir Rintel              - nvidia,tegra124-uart
110e69f5dc6SLubomir Rintel              - nvidia,tegra186-uart
111e69f5dc6SLubomir Rintel              - nvidia,tegra194-uart
112e69f5dc6SLubomir Rintel              - nvidia,tegra210-uart
113e69f5dc6SLubomir Rintel          - const: nvidia,tegra20-uart
114e69f5dc6SLubomir Rintel
115e69f5dc6SLubomir Rintel  reg:
116e69f5dc6SLubomir Rintel    maxItems: 1
117e69f5dc6SLubomir Rintel
118e69f5dc6SLubomir Rintel  interrupts:
119e69f5dc6SLubomir Rintel    maxItems: 1
120e69f5dc6SLubomir Rintel
121e69f5dc6SLubomir Rintel  clock-frequency: true
122e69f5dc6SLubomir Rintel
123e69f5dc6SLubomir Rintel  clocks:
124e69f5dc6SLubomir Rintel    maxItems: 1
125e69f5dc6SLubomir Rintel
126e69f5dc6SLubomir Rintel  resets:
127e69f5dc6SLubomir Rintel    maxItems: 1
128e69f5dc6SLubomir Rintel
129e69f5dc6SLubomir Rintel  current-speed:
130d69c6dddSRob Herring    $ref: /schemas/types.yaml#/definitions/uint32
131e69f5dc6SLubomir Rintel    description: The current active speed of the UART.
132e69f5dc6SLubomir Rintel
133e69f5dc6SLubomir Rintel  reg-offset:
134e69f5dc6SLubomir Rintel    description: |
135e69f5dc6SLubomir Rintel      Offset to apply to the mapbase from the start of the registers.
136e69f5dc6SLubomir Rintel
137e69f5dc6SLubomir Rintel  reg-shift:
138e69f5dc6SLubomir Rintel    description: Quantity to shift the register offsets by.
139e69f5dc6SLubomir Rintel
140e69f5dc6SLubomir Rintel  reg-io-width:
141e69f5dc6SLubomir Rintel    description: |
142e69f5dc6SLubomir Rintel      The size (in bytes) of the IO accesses that should be performed on the
143e69f5dc6SLubomir Rintel      device. There are some systems that require 32-bit accesses to the
144e69f5dc6SLubomir Rintel      UART (e.g. TI davinci).
145e69f5dc6SLubomir Rintel
146e69f5dc6SLubomir Rintel  used-by-rtas:
147e69f5dc6SLubomir Rintel    type: boolean
148e69f5dc6SLubomir Rintel    description: |
149e69f5dc6SLubomir Rintel      Set to indicate that the port is in use by the OpenFirmware RTAS and
150e69f5dc6SLubomir Rintel      should not be registered.
151e69f5dc6SLubomir Rintel
152e69f5dc6SLubomir Rintel  no-loopback-test:
153e69f5dc6SLubomir Rintel    type: boolean
154e69f5dc6SLubomir Rintel    description: |
155e69f5dc6SLubomir Rintel      Set to indicate that the port does not implement loopback test mode.
156e69f5dc6SLubomir Rintel
157e69f5dc6SLubomir Rintel  fifo-size:
158d69c6dddSRob Herring    $ref: /schemas/types.yaml#/definitions/uint32
159e69f5dc6SLubomir Rintel    description: The fifo size of the UART.
160e69f5dc6SLubomir Rintel
161e69f5dc6SLubomir Rintel  auto-flow-control:
162e69f5dc6SLubomir Rintel    type: boolean
163e69f5dc6SLubomir Rintel    description: |
164e69f5dc6SLubomir Rintel      One way to enable automatic flow control support. The driver is
165e69f5dc6SLubomir Rintel      allowed to detect support for the capability even without this
166e69f5dc6SLubomir Rintel      property.
167e69f5dc6SLubomir Rintel
168e69f5dc6SLubomir Rintel  tx-threshold:
169d69c6dddSRob Herring    $ref: /schemas/types.yaml#/definitions/uint32
170e69f5dc6SLubomir Rintel    description: |
171e69f5dc6SLubomir Rintel      Specify the TX FIFO low water indication for parts with programmable
172e69f5dc6SLubomir Rintel      TX FIFO thresholds.
173e69f5dc6SLubomir Rintel
174e69f5dc6SLubomir Rintel  overrun-throttle-ms:
175e69f5dc6SLubomir Rintel    description: |
176e69f5dc6SLubomir Rintel      How long to pause uart rx when input overrun is encountered.
177e69f5dc6SLubomir Rintel
178e69f5dc6SLubomir Rintel  rts-gpios: true
179e69f5dc6SLubomir Rintel  cts-gpios: true
180e69f5dc6SLubomir Rintel  dtr-gpios: true
181e69f5dc6SLubomir Rintel  dsr-gpios: true
182e69f5dc6SLubomir Rintel  rng-gpios: true
183e69f5dc6SLubomir Rintel  dcd-gpios: true
184e69f5dc6SLubomir Rintel
185e69f5dc6SLubomir Rintel  aspeed,sirq-polarity-sense:
186e69f5dc6SLubomir Rintel    $ref: /schemas/types.yaml#/definitions/phandle-array
187e69f5dc6SLubomir Rintel    description: |
188e69f5dc6SLubomir Rintel      Phandle to aspeed,ast2500-scu compatible syscon alongside register
189e69f5dc6SLubomir Rintel      offset and bit number to identify how the SIRQ polarity should be
190e69f5dc6SLubomir Rintel      configured. One possible data source is the LPC/eSPI mode bit. Only
191e69f5dc6SLubomir Rintel      applicable to aspeed,ast2500-vuart.
192e69f5dc6SLubomir Rintel
193e69f5dc6SLubomir Rintelrequired:
194e69f5dc6SLubomir Rintel  - reg
195e69f5dc6SLubomir Rintel  - interrupts
196e69f5dc6SLubomir Rintel
197e69f5dc6SLubomir RintelunevaluatedProperties: false
198e69f5dc6SLubomir Rintel
199e69f5dc6SLubomir Rintelexamples:
200e69f5dc6SLubomir Rintel  - |
201e69f5dc6SLubomir Rintel    serial@80230000 {
202e69f5dc6SLubomir Rintel        compatible = "ns8250";
203e69f5dc6SLubomir Rintel        reg = <0x80230000 0x100>;
204e69f5dc6SLubomir Rintel        interrupts = <10>;
205e69f5dc6SLubomir Rintel        reg-shift = <2>;
206e69f5dc6SLubomir Rintel        clock-frequency = <48000000>;
207e69f5dc6SLubomir Rintel    };
208e69f5dc6SLubomir Rintel  - |
209e69f5dc6SLubomir Rintel    #include <dt-bindings/gpio/gpio.h>
210e69f5dc6SLubomir Rintel    serial@49042000 {
211e69f5dc6SLubomir Rintel        compatible = "andestech,uart16550", "ns16550a";
212e69f5dc6SLubomir Rintel        reg = <0x49042000 0x400>;
213e69f5dc6SLubomir Rintel        interrupts = <80>;
214e69f5dc6SLubomir Rintel        clock-frequency = <48000000>;
215e69f5dc6SLubomir Rintel        cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
216e69f5dc6SLubomir Rintel        rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
217e69f5dc6SLubomir Rintel        dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
218e69f5dc6SLubomir Rintel        dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
219e69f5dc6SLubomir Rintel        dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
220e69f5dc6SLubomir Rintel        rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
221e69f5dc6SLubomir Rintel    };
222e69f5dc6SLubomir Rintel  - |
223e69f5dc6SLubomir Rintel    #include <dt-bindings/clock/aspeed-clock.h>
224e69f5dc6SLubomir Rintel    serial@1e787000 {
225e69f5dc6SLubomir Rintel        compatible = "aspeed,ast2500-vuart";
226e69f5dc6SLubomir Rintel        reg = <0x1e787000 0x40>;
227e69f5dc6SLubomir Rintel        reg-shift = <2>;
228e69f5dc6SLubomir Rintel        interrupts = <8>;
229e69f5dc6SLubomir Rintel        clocks = <&syscon ASPEED_CLK_APB>;
230e69f5dc6SLubomir Rintel        no-loopback-test;
231e69f5dc6SLubomir Rintel        aspeed,sirq-polarity-sense = <&syscon 0x70 25>;
232e69f5dc6SLubomir Rintel    };
233e69f5dc6SLubomir Rintel
234e69f5dc6SLubomir Rintel...
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