1* HiSilicon SAS controller 2 3The HiSilicon SAS controller supports SAS/SATA. 4 5Main node required properties: 6 - compatible : value should be as follows: 7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset 8 - sas-addr : array of 8 bytes for host SAS address 9 - reg : Address and length of the SAS register 10 - hisilicon,sas-syscon: phandle of syscon used for sas control 11 - ctrl-reset-reg : offset to controller reset register in ctrl reg 12 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg 13 - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg 14 - queue-count : number of delivery and completion queues in the controller 15 - phy-count : number of phys accessible by the controller 16 - interrupts : Interrupts for phys, completion queues, and fatal 17 sources; the interrupts are ordered in 3 groups, as follows: 18 - Phy interrupts 19 - Completion queue interrupts 20 - Fatal interrupts 21 Phy interrupts : Each phy has 3 interrupt sources: 22 - broadcast 23 - phyup 24 - abnormal 25 The phy interrupts are ordered into groups of 3 per phy 26 (broadcast, phyup, and abnormal) in increasing order. 27 Completion queue interrupts : each completion queue has 1 28 interrupt source. 29 The interrupts are ordered in increasing order. 30 Fatal interrupts : the fatal interrupts are ordered as follows: 31 - ECC 32 - AXI bus 33 34Example: 35 sas0: sas@c1000000 { 36 compatible = "hisilicon,hip05-sas-v1"; 37 sas-addr = [50 01 88 20 16 00 00 0a]; 38 reg = <0x0 0xc1000000 0x0 0x10000>; 39 hisilicon,sas-syscon = <&pcie_sas>; 40 ctrl-reset-reg = <0xa60>; 41 ctrl-reset-sts-reg = <0x5a30>; 42 ctrl-clock-ena-reg = <0x338>; 43 queue-count = <32>; 44 phy-count = <8>; 45 dma-coherent; 46 interrupt-parent = <&mbigen_dsa>; 47 interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */ 48 <269 4>,<273 4>,<274 4>,/* phy1 */ 49 <279 4>,<283 4>,<284 4>,/* phy2 */ 50 <289 4>,<293 4>,<294 4>,/* phy3 */ 51 <299 4>,<303 4>,<304 4>,/* phy4 */ 52 <309 4>,<313 4>,<314 4>,/* phy5 */ 53 <319 4>,<323 4>,<324 4>,/* phy6 */ 54 <329 4>,<333 4>,<334 4>,/* phy7 */ 55 <336 1>,<337 1>,<338 1>,/* cq0-2 */ 56 <339 1>,<340 1>,<341 1>,/* cq3-5 */ 57 <342 1>,<343 1>,<344 1>,/* cq6-8 */ 58 <345 1>,<346 1>,<347 1>,/* cq9-11 */ 59 <348 1>,<349 1>,<350 1>,/* cq12-14 */ 60 <351 1>,<352 1>,<353 1>,/* cq15-17 */ 61 <354 1>,<355 1>,<356 1>,/* cq18-20 */ 62 <357 1>,<358 1>,<359 1>,/* cq21-23 */ 63 <360 1>,<361 1>,<362 1>,/* cq24-26 */ 64 <363 1>,<364 1>,<365 1>,/* cq27-29 */ 65 <366 1>,<367 1>/* cq30-31 */ 66 <376 4>,/* fatal ecc */ 67 <381 4>;/* fatal axi */ 68 status = "disabled"; 69 }; 70