1* HiSilicon SAS controller
2
3The HiSilicon SAS controller supports SAS/SATA.
4
5Main node required properties:
6  - compatible : value should be as follows:
7	(a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8	(b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9  - sas-addr : array of 8 bytes for host SAS address
10  - reg : Address and length of the SAS register
11  - hisilicon,sas-syscon: phandle of syscon used for sas control
12  - ctrl-reset-reg : offset to controller reset register in ctrl reg
13  - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
14  - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
15  - queue-count : number of delivery and completion queues in the controller
16  - phy-count : number of phys accessible by the controller
17  - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
18		sources; the interrupts are ordered in 3 groups, as follows:
19			- Phy interrupts
20			- Completion queue interrupts
21			- Fatal interrupts
22		Phy interrupts : Each phy has 3 interrupt sources:
23			- broadcast
24			- phyup
25			- abnormal
26		The phy interrupts are ordered into groups of 3 per phy
27		(broadcast, phyup, and abnormal) in increasing order.
28		Completion queue interrupts : each completion queue has 1
29			interrupt source.
30			The interrupts are ordered in increasing order.
31		Fatal interrupts : the fatal interrupts are ordered as follows:
32			- ECC
33			- AXI bus
34		For v2 hw: Interrupts for phys, Sata, and completion queues;
35		the interrupts are ordered in 3 groups, as follows:
36			- Phy interrupts
37			- Sata interrupts
38			- Completion queue interrupts
39		Phy interrupts : Each controller has 2 phy interrupts:
40			- phy up/down
41			- channel interrupt
42		Sata interrupts : Each phy on the controller has 1 Sata
43			interrupt. The interrupts are ordered in increasing
44			order.
45		Completion queue interrupts : each completion queue has 1
46			interrupt source. The interrupts are ordered in
47			increasing order.
48
49Optional main node properties:
50 - hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
51			    "am-max-transmissions" limitation.
52
53Example:
54	sas0: sas@c1000000 {
55		compatible = "hisilicon,hip05-sas-v1";
56		sas-addr = [50 01 88 20 16 00 00 0a];
57		reg = <0x0 0xc1000000 0x0 0x10000>;
58		hisilicon,sas-syscon = <&pcie_sas>;
59		ctrl-reset-reg = <0xa60>;
60		ctrl-reset-sts-reg = <0x5a30>;
61		ctrl-clock-ena-reg = <0x338>;
62		queue-count = <32>;
63		phy-count = <8>;
64		dma-coherent;
65		interrupt-parent = <&mbigen_dsa>;
66		interrupts =    <259 4>,<263 4>,<264 4>,/* phy0 */
67				<269 4>,<273 4>,<274 4>,/* phy1 */
68				<279 4>,<283 4>,<284 4>,/* phy2 */
69				<289 4>,<293 4>,<294 4>,/* phy3 */
70				<299 4>,<303 4>,<304 4>,/* phy4 */
71				<309 4>,<313 4>,<314 4>,/* phy5 */
72				<319 4>,<323 4>,<324 4>,/* phy6 */
73				<329 4>,<333 4>,<334 4>,/* phy7 */
74				<336 1>,<337 1>,<338 1>,/* cq0-2 */
75				<339 1>,<340 1>,<341 1>,/* cq3-5 */
76				<342 1>,<343 1>,<344 1>,/* cq6-8 */
77				<345 1>,<346 1>,<347 1>,/* cq9-11 */
78				<348 1>,<349 1>,<350 1>,/* cq12-14 */
79				<351 1>,<352 1>,<353 1>,/* cq15-17 */
80				<354 1>,<355 1>,<356 1>,/* cq18-20 */
81				<357 1>,<358 1>,<359 1>,/* cq21-23 */
82				<360 1>,<361 1>,<362 1>,/* cq24-26 */
83				<363 1>,<364 1>,<365 1>,/* cq27-29 */
84				<366 1>,<367 1>/* cq30-31 */
85				<376 4>,/* fatal ecc */
86				<381 4>;/* fatal axi */
87		status = "disabled";
88	};
89