1*1a60317bSFabien Parent# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*1a60317bSFabien Parent%YAML 1.2 3*1a60317bSFabien Parent--- 4*1a60317bSFabien Parent$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#" 5*1a60317bSFabien Parent$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*1a60317bSFabien Parent 7*1a60317bSFabien Parenttitle: MediaTek Random number generator 8*1a60317bSFabien Parent 9*1a60317bSFabien Parentmaintainers: 10*1a60317bSFabien Parent - Sean Wang <sean.wang@mediatek.com> 11*1a60317bSFabien Parent 12*1a60317bSFabien Parentproperties: 13*1a60317bSFabien Parent $nodename: 14*1a60317bSFabien Parent pattern: "^rng@[0-9a-f]+$" 15*1a60317bSFabien Parent 16*1a60317bSFabien Parent compatible: 17*1a60317bSFabien Parent oneOf: 18*1a60317bSFabien Parent - enum: 19*1a60317bSFabien Parent - mediatek,mt7623-rng 20*1a60317bSFabien Parent - items: 21*1a60317bSFabien Parent - enum: 22*1a60317bSFabien Parent - mediatek,mt7622-rng 23*1a60317bSFabien Parent - mediatek,mt7629-rng 24*1a60317bSFabien Parent - mediatek,mt8516-rng 25*1a60317bSFabien Parent - const: mediatek,mt7623-rng 26*1a60317bSFabien Parent 27*1a60317bSFabien Parent reg: 28*1a60317bSFabien Parent maxItems: 1 29*1a60317bSFabien Parent 30*1a60317bSFabien Parent clocks: 31*1a60317bSFabien Parent maxItems: 1 32*1a60317bSFabien Parent 33*1a60317bSFabien Parent clock-names: 34*1a60317bSFabien Parent items: 35*1a60317bSFabien Parent - const: rng 36*1a60317bSFabien Parent 37*1a60317bSFabien Parentrequired: 38*1a60317bSFabien Parent - compatible 39*1a60317bSFabien Parent - reg 40*1a60317bSFabien Parent - clocks 41*1a60317bSFabien Parent - clock-names 42*1a60317bSFabien Parent 43*1a60317bSFabien ParentadditionalProperties: false 44*1a60317bSFabien Parent 45*1a60317bSFabien Parentexamples: 46*1a60317bSFabien Parent - | 47*1a60317bSFabien Parent #include <dt-bindings/clock/mt2701-clk.h> 48*1a60317bSFabien Parent rng: rng@1020f000 { 49*1a60317bSFabien Parent compatible = "mediatek,mt7623-rng"; 50*1a60317bSFabien Parent reg = <0x1020f000 0x1000>; 51*1a60317bSFabien Parent clocks = <&infracfg CLK_INFRA_TRNG>; 52*1a60317bSFabien Parent clock-names = "rng"; 53*1a60317bSFabien Parent }; 54