11a60317bSFabien Parent# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 21a60317bSFabien Parent%YAML 1.2 31a60317bSFabien Parent--- 4*66ae0535SRob Herring$id: http://devicetree.org/schemas/rng/mtk-rng.yaml# 5*66ae0535SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 61a60317bSFabien Parent 71a60317bSFabien Parenttitle: MediaTek Random number generator 81a60317bSFabien Parent 91a60317bSFabien Parentmaintainers: 101a60317bSFabien Parent - Sean Wang <sean.wang@mediatek.com> 111a60317bSFabien Parent 121a60317bSFabien Parentproperties: 131a60317bSFabien Parent $nodename: 141a60317bSFabien Parent pattern: "^rng@[0-9a-f]+$" 151a60317bSFabien Parent 161a60317bSFabien Parent compatible: 171a60317bSFabien Parent oneOf: 181a60317bSFabien Parent - enum: 191a60317bSFabien Parent - mediatek,mt7623-rng 201a60317bSFabien Parent - items: 211a60317bSFabien Parent - enum: 221a60317bSFabien Parent - mediatek,mt7622-rng 231a60317bSFabien Parent - mediatek,mt7629-rng 246ef02f9cSSam Shih - mediatek,mt7986-rng 2570c1fc34SFabien Parent - mediatek,mt8365-rng 261a60317bSFabien Parent - mediatek,mt8516-rng 271a60317bSFabien Parent - const: mediatek,mt7623-rng 281a60317bSFabien Parent 291a60317bSFabien Parent reg: 301a60317bSFabien Parent maxItems: 1 311a60317bSFabien Parent 321a60317bSFabien Parent clocks: 331a60317bSFabien Parent maxItems: 1 341a60317bSFabien Parent 351a60317bSFabien Parent clock-names: 361a60317bSFabien Parent items: 371a60317bSFabien Parent - const: rng 381a60317bSFabien Parent 391a60317bSFabien Parentrequired: 401a60317bSFabien Parent - compatible 411a60317bSFabien Parent - reg 421a60317bSFabien Parent - clocks 431a60317bSFabien Parent - clock-names 441a60317bSFabien Parent 451a60317bSFabien ParentadditionalProperties: false 461a60317bSFabien Parent 471a60317bSFabien Parentexamples: 481a60317bSFabien Parent - | 491a60317bSFabien Parent #include <dt-bindings/clock/mt2701-clk.h> 501a60317bSFabien Parent rng: rng@1020f000 { 511a60317bSFabien Parent compatible = "mediatek,mt7623-rng"; 521a60317bSFabien Parent reg = <0x1020f000 0x1000>; 531a60317bSFabien Parent clocks = <&infracfg CLK_INFRA_TRNG>; 541a60317bSFabien Parent clock-names = "rng"; 551a60317bSFabien Parent }; 56