1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/extensions.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V ISA extensions
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12  - Conor Dooley <conor@kernel.org>
13
14description: |
15  RISC-V has a large number of extensions, some of which are "standard"
16  extensions, meaning they are ratified by RISC-V International, and others
17  are "vendor" extensions.
18  This document defines properties that indicate whether a hart supports a
19  given extension.
20
21  Once a standard extension has been ratified, no changes in behaviour can be
22  made without the creation of a new extension.
23  The properties for standard extensions therefore map to their originally
24  ratified states, with the exception of the I, Zicntr & Zihpm extensions.
25  See the "i" property for more information.
26
27select:
28  properties:
29    compatible:
30      contains:
31        const: riscv
32
33properties:
34  riscv,isa:
35    description:
36      Identifies the specific RISC-V instruction set architecture
37      supported by the hart.  These are documented in the RISC-V
38      User-Level ISA document, available from
39      https://riscv.org/specifications/
40
41      Due to revisions of the ISA specification, some deviations
42      have arisen over time.
43      Notably, riscv,isa was defined prior to the creation of the
44      Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
45      implies "zicntr_zicsr_zifencei_zihpm".
46
47      While the isa strings in ISA specification are case
48      insensitive, letters in the riscv,isa string must be all
49      lowercase.
50    $ref: /schemas/types.yaml#/definitions/string
51    pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
52    deprecated: true
53
54  riscv,isa-base:
55    description:
56      The base ISA implemented by this hart, as described by the 20191213
57      version of the unprivileged ISA specification.
58    enum:
59      - rv32i
60      - rv64i
61
62  riscv,isa-extensions:
63    $ref: /schemas/types.yaml#/definitions/string-array
64    minItems: 1
65    description: Extensions supported by the hart.
66    items:
67      anyOf:
68        # single letter extensions, in canonical order
69        - const: i
70          description: |
71            The base integer instruction set, as ratified in the 20191213
72            version of the unprivileged ISA specification.
73
74            This does not include Chapter 10, "Counters", which was moved into
75            the Zicntr and Zihpm extensions after the ratification of the
76            20191213 version of the unprivileged specification.
77
78        - const: m
79          description:
80            The standard M extension for integer multiplication and division, as
81            ratified in the 20191213 version of the unprivileged ISA
82            specification.
83
84        - const: a
85          description:
86            The standard A extension for atomic instructions, as ratified in the
87            20191213 version of the unprivileged ISA specification.
88
89        - const: f
90          description:
91            The standard F extension for single-precision floating point, as
92            ratified in the 20191213 version of the unprivileged ISA
93            specification.
94
95        - const: d
96          description:
97            The standard D extension for double-precision floating-point, as
98            ratified in the 20191213 version of the unprivileged ISA
99            specification.
100
101        - const: q
102          description:
103            The standard Q extension for quad-precision floating-point, as
104            ratified in the 20191213 version of the unprivileged ISA
105            specification.
106
107        - const: c
108          description:
109            The standard C extension for compressed instructions, as ratified in
110            the 20191213 version of the unprivileged ISA specification.
111
112        - const: v
113          description:
114            The standard V extension for vector operations, as ratified
115            in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116            encoding") of the riscv-v-spec.
117
118        - const: h
119          description:
120            The standard H extension for hypervisors as ratified in the 20191213
121            version of the privileged ISA specification.
122
123        # multi-letter extensions, sorted alphanumerically
124        - const: smaia
125          description: |
126            The standard Smaia supervisor-level extension for the advanced
127            interrupt architecture for machine-mode-visible csr and behavioural
128            changes to interrupts as frozen at commit ccbddab ("Merge pull
129            request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
130
131        - const: ssaia
132          description: |
133            The standard Ssaia supervisor-level extension for the advanced
134            interrupt architecture for supervisor-mode-visible csr and
135            behavioural changes to interrupts as frozen at commit ccbddab
136            ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
137
138        - const: sscofpmf
139          description: |
140            The standard Sscofpmf supervisor-level extension for count overflow
141            and mode-based filtering as ratified at commit 01d1df0 ("Add ability
142            to manually trigger workflow. (#2)") of riscv-count-overflow.
143
144        - const: sstc
145          description: |
146            The standard Sstc supervisor-level extension for time compare as
147            ratified at commit 3f9ed34 ("Add ability to manually trigger
148            workflow. (#2)") of riscv-time-compare.
149
150        - const: svinval
151          description:
152            The standard Svinval supervisor-level extension for fine-grained
153            address-translation cache invalidation as ratified in the 20191213
154            version of the privileged ISA specification.
155
156        - const: svnapot
157          description:
158            The standard Svnapot supervisor-level extensions for napot
159            translation contiguity as ratified in the 20191213 version of the
160            privileged ISA specification.
161
162        - const: svpbmt
163          description:
164            The standard Svpbmt supervisor-level extensions for page-based
165            memory types as ratified in the 20191213 version of the privileged
166            ISA specification.
167
168        - const: zba
169          description: |
170            The standard Zba bit-manipulation extension for address generation
171            acceleration instructions as ratified at commit 6d33919 ("Merge pull
172            request #158 from hirooih/clmul-fix-loop-end-condition") of
173            riscv-bitmanip.
174
175        - const: zbb
176          description: |
177            The standard Zbb bit-manipulation extension for basic bit-manipulation
178            as ratified at commit 6d33919 ("Merge pull request #158 from
179            hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
180
181        - const: zbc
182          description: |
183            The standard Zbc bit-manipulation extension for carry-less
184            multiplication as ratified at commit 6d33919 ("Merge pull request
185            #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
186
187        - const: zbs
188          description: |
189            The standard Zbs bit-manipulation extension for single-bit
190            instructions as ratified at commit 6d33919 ("Merge pull request #158
191            from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
192
193        - const: zicbom
194          description:
195            The standard Zicbom extension for base cache management operations as
196            ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
197
198        - const: zicbop
199          description:
200            The standard Zicbop extension for cache-block prefetch instructions
201            as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
202            riscv-CMOs.
203
204        - const: zicboz
205          description:
206            The standard Zicboz extension for cache-block zeroing as ratified
207            in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
208
209        - const: zicntr
210          description:
211            The standard Zicntr extension for base counters and timers, as
212            ratified in the 20191213 version of the unprivileged ISA
213            specification.
214
215        - const: zicsr
216          description: |
217            The standard Zicsr extension for control and status register
218            instructions, as ratified in the 20191213 version of the
219            unprivileged ISA specification.
220
221            This does not include Chapter 10, "Counters", which documents
222            special case read-only CSRs, that were moved into the Zicntr and
223            Zihpm extensions after the ratification of the 20191213 version of
224            the unprivileged specification.
225
226        - const: zifencei
227          description:
228            The standard Zifencei extension for instruction-fetch fence, as
229            ratified in the 20191213 version of the unprivileged ISA
230            specification.
231
232        - const: zihintpause
233          description:
234            The standard Zihintpause extension for pause hints, as ratified in
235            commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
236
237        - const: zihpm
238          description:
239            The standard Zihpm extension for hardware performance counters, as
240            ratified in the 20191213 version of the unprivileged ISA
241            specification.
242
243        - const: ztso
244          description:
245            The standard Ztso extension for total store ordering, as ratified
246            in commit 2e5236 ("Ztso is now ratified.") of the
247            riscv-isa-manual.
248
249additionalProperties: true
250...
251