1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V bindings for 'cpus' DT nodes
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12
13description: |
14  This document uses some terminology common to the RISC-V community
15  that is not widely used, the definitions of which are listed here:
16
17  hart: A hardware execution context, which contains all the state
18  mandated by the RISC-V ISA: a PC and some registers.  This
19  terminology is designed to disambiguate software's view of execution
20  contexts from any particular microarchitectural implementation
21  strategy.  For example, an Intel laptop containing one socket with
22  two cores, each of which has two hyperthreads, could be described as
23  having four harts.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - sifive,rocket0
30          - sifive,e5
31          - sifive,e51
32          - sifive,u54-mc
33          - sifive,u54
34          - sifive,u5
35      - const: riscv
36    description:
37      Identifies that the hart uses the RISC-V instruction set
38      and identifies the type of the hart.
39
40  mmu-type:
41    allOf:
42      - $ref: "/schemas/types.yaml#/definitions/string"
43      - enum:
44          - riscv,sv32
45          - riscv,sv39
46          - riscv,sv48
47    description:
48      Identifies the MMU address translation mode used on this
49      hart.  These values originate from the RISC-V Privileged
50      Specification document, available from
51      https://riscv.org/specifications/
52
53  riscv,isa:
54    allOf:
55      - $ref: "/schemas/types.yaml#/definitions/string"
56      - enum:
57          - rv64imac
58          - rv64imafdc
59    description:
60      Identifies the specific RISC-V instruction set architecture
61      supported by the hart.  These are documented in the RISC-V
62      User-Level ISA document, available from
63      https://riscv.org/specifications/
64
65      While the isa strings in ISA specification are case
66      insensitive, letters in the riscv,isa string must be all
67      lowercase to simplify parsing.
68
69  timebase-frequency:
70    type: integer
71    minimum: 1
72    description:
73      Specifies the clock frequency of the system timer in Hz.
74      This value is common to all harts on a single system image.
75
76  interrupt-controller:
77    type: object
78    description: Describes the CPU's local interrupt controller
79
80    properties:
81      '#interrupt-cells':
82        const: 1
83
84      compatible:
85        const: riscv,cpu-intc
86
87      interrupt-controller: true
88
89    required:
90      - '#interrupt-cells'
91      - compatible
92      - interrupt-controller
93
94required:
95  - riscv,isa
96  - timebase-frequency
97  - interrupt-controller
98
99examples:
100  - |
101    // Example 1: SiFive Freedom U540G Development Kit
102    cpus {
103        #address-cells = <1>;
104        #size-cells = <0>;
105        timebase-frequency = <1000000>;
106        cpu@0 {
107                clock-frequency = <0>;
108                compatible = "sifive,rocket0", "riscv";
109                device_type = "cpu";
110                i-cache-block-size = <64>;
111                i-cache-sets = <128>;
112                i-cache-size = <16384>;
113                reg = <0>;
114                riscv,isa = "rv64imac";
115                cpu_intc0: interrupt-controller {
116                        #interrupt-cells = <1>;
117                        compatible = "riscv,cpu-intc";
118                        interrupt-controller;
119                };
120        };
121        cpu@1 {
122                clock-frequency = <0>;
123                compatible = "sifive,rocket0", "riscv";
124                d-cache-block-size = <64>;
125                d-cache-sets = <64>;
126                d-cache-size = <32768>;
127                d-tlb-sets = <1>;
128                d-tlb-size = <32>;
129                device_type = "cpu";
130                i-cache-block-size = <64>;
131                i-cache-sets = <64>;
132                i-cache-size = <32768>;
133                i-tlb-sets = <1>;
134                i-tlb-size = <32>;
135                mmu-type = "riscv,sv39";
136                reg = <1>;
137                riscv,isa = "rv64imafdc";
138                tlb-split;
139                cpu_intc1: interrupt-controller {
140                        #interrupt-cells = <1>;
141                        compatible = "riscv,cpu-intc";
142                        interrupt-controller;
143                };
144        };
145    };
146
147  - |
148    // Example 2: Spike ISA Simulator with 1 Hart
149    cpus {
150        #address-cells = <1>;
151        #size-cells = <0>;
152        cpu@0 {
153                device_type = "cpu";
154                reg = <0>;
155                compatible = "riscv";
156                riscv,isa = "rv64imafdc";
157                mmu-type = "riscv,sv48";
158                interrupt-controller {
159                        #interrupt-cells = <1>;
160                        interrupt-controller;
161                        compatible = "riscv,cpu-intc";
162                };
163        };
164    };
165...
166