1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L USBPHY Control
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12description:
13  The RZ/G2L USBPHY Control mainly controls reset and power down of the
14  USB/PHY.
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
21      - const: renesas,rzg2l-usbphy-ctrl
22
23  reg:
24    maxItems: 1
25
26  clocks:
27    maxItems: 1
28
29  resets:
30    maxItems: 1
31
32  power-domains:
33    maxItems: 1
34
35  '#reset-cells':
36    const: 1
37    description: |
38      The phandle's argument in the reset specifier is the PHY reset associated
39      with the USB port.
40      0 = Port 1 Phy reset
41      1 = Port 2 Phy reset
42
43required:
44  - compatible
45  - reg
46  - clocks
47  - resets
48  - power-domains
49  - '#reset-cells'
50
51additionalProperties: false
52
53examples:
54  - |
55    #include <dt-bindings/clock/r9a07g044-cpg.h>
56
57    phyrst: usbphy-ctrl@11c40000 {
58        compatible = "renesas,r9a07g044-usbphy-ctrl",
59                     "renesas,rzg2l-usbphy-ctrl";
60        reg = <0x11c40000 0x10000>;
61        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
62        resets = <&cpg R9A07G044_USB_PRESETN>;
63        power-domains = <&cpg>;
64        #reset-cells = <1>;
65    };
66