118931afeSBiju Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 218931afeSBiju Das%YAML 1.2 318931afeSBiju Das--- 418931afeSBiju Das$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# 518931afeSBiju Das$schema: http://devicetree.org/meta-schemas/core.yaml# 618931afeSBiju Das 7*f866a7aeSLad Prabhakartitle: Renesas RZ/{G2L,V2L} USBPHY Control 818931afeSBiju Das 918931afeSBiju Dasmaintainers: 1018931afeSBiju Das - Biju Das <biju.das.jz@bp.renesas.com> 1118931afeSBiju Das 1218931afeSBiju Dasdescription: 1318931afeSBiju Das The RZ/G2L USBPHY Control mainly controls reset and power down of the 1418931afeSBiju Das USB/PHY. 1518931afeSBiju Das 1618931afeSBiju Dasproperties: 1718931afeSBiju Das compatible: 1818931afeSBiju Das items: 1918931afeSBiju Das - enum: 2018931afeSBiju Das - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 21*f866a7aeSLad Prabhakar - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 2218931afeSBiju Das - const: renesas,rzg2l-usbphy-ctrl 2318931afeSBiju Das 2418931afeSBiju Das reg: 2518931afeSBiju Das maxItems: 1 2618931afeSBiju Das 2718931afeSBiju Das clocks: 2818931afeSBiju Das maxItems: 1 2918931afeSBiju Das 3018931afeSBiju Das resets: 3118931afeSBiju Das maxItems: 1 3218931afeSBiju Das 3318931afeSBiju Das power-domains: 3418931afeSBiju Das maxItems: 1 3518931afeSBiju Das 3618931afeSBiju Das '#reset-cells': 3718931afeSBiju Das const: 1 3818931afeSBiju Das description: | 3918931afeSBiju Das The phandle's argument in the reset specifier is the PHY reset associated 4018931afeSBiju Das with the USB port. 4118931afeSBiju Das 0 = Port 1 Phy reset 4218931afeSBiju Das 1 = Port 2 Phy reset 4318931afeSBiju Das 4418931afeSBiju Dasrequired: 4518931afeSBiju Das - compatible 4618931afeSBiju Das - reg 4718931afeSBiju Das - clocks 4818931afeSBiju Das - resets 4918931afeSBiju Das - power-domains 5018931afeSBiju Das - '#reset-cells' 5118931afeSBiju Das 5218931afeSBiju DasadditionalProperties: false 5318931afeSBiju Das 5418931afeSBiju Dasexamples: 5518931afeSBiju Das - | 5618931afeSBiju Das #include <dt-bindings/clock/r9a07g044-cpg.h> 5718931afeSBiju Das 5818931afeSBiju Das phyrst: usbphy-ctrl@11c40000 { 5918931afeSBiju Das compatible = "renesas,r9a07g044-usbphy-ctrl", 6018931afeSBiju Das "renesas,rzg2l-usbphy-ctrl"; 6118931afeSBiju Das reg = <0x11c40000 0x10000>; 6218931afeSBiju Das clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 6318931afeSBiju Das resets = <&cpg R9A07G044_USB_PRESETN>; 6418931afeSBiju Das power-domains = <&cpg>; 6518931afeSBiju Das #reset-cells = <1>; 6618931afeSBiju Das }; 67