1*18931afeSBiju Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*18931afeSBiju Das%YAML 1.2 3*18931afeSBiju Das--- 4*18931afeSBiju Das$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# 5*18931afeSBiju Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*18931afeSBiju Das 7*18931afeSBiju Dastitle: Renesas RZ/G2L USBPHY Control 8*18931afeSBiju Das 9*18931afeSBiju Dasmaintainers: 10*18931afeSBiju Das - Biju Das <biju.das.jz@bp.renesas.com> 11*18931afeSBiju Das 12*18931afeSBiju Dasdescription: 13*18931afeSBiju Das The RZ/G2L USBPHY Control mainly controls reset and power down of the 14*18931afeSBiju Das USB/PHY. 15*18931afeSBiju Das 16*18931afeSBiju Dasproperties: 17*18931afeSBiju Das compatible: 18*18931afeSBiju Das items: 19*18931afeSBiju Das - enum: 20*18931afeSBiju Das - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 21*18931afeSBiju Das - const: renesas,rzg2l-usbphy-ctrl 22*18931afeSBiju Das 23*18931afeSBiju Das reg: 24*18931afeSBiju Das maxItems: 1 25*18931afeSBiju Das 26*18931afeSBiju Das clocks: 27*18931afeSBiju Das maxItems: 1 28*18931afeSBiju Das 29*18931afeSBiju Das resets: 30*18931afeSBiju Das maxItems: 1 31*18931afeSBiju Das 32*18931afeSBiju Das power-domains: 33*18931afeSBiju Das maxItems: 1 34*18931afeSBiju Das 35*18931afeSBiju Das '#reset-cells': 36*18931afeSBiju Das const: 1 37*18931afeSBiju Das description: | 38*18931afeSBiju Das The phandle's argument in the reset specifier is the PHY reset associated 39*18931afeSBiju Das with the USB port. 40*18931afeSBiju Das 0 = Port 1 Phy reset 41*18931afeSBiju Das 1 = Port 2 Phy reset 42*18931afeSBiju Das 43*18931afeSBiju Dasrequired: 44*18931afeSBiju Das - compatible 45*18931afeSBiju Das - reg 46*18931afeSBiju Das - clocks 47*18931afeSBiju Das - resets 48*18931afeSBiju Das - power-domains 49*18931afeSBiju Das - '#reset-cells' 50*18931afeSBiju Das 51*18931afeSBiju DasadditionalProperties: false 52*18931afeSBiju Das 53*18931afeSBiju Dasexamples: 54*18931afeSBiju Das - | 55*18931afeSBiju Das #include <dt-bindings/clock/r9a07g044-cpg.h> 56*18931afeSBiju Das 57*18931afeSBiju Das phyrst: usbphy-ctrl@11c40000 { 58*18931afeSBiju Das compatible = "renesas,r9a07g044-usbphy-ctrl", 59*18931afeSBiju Das "renesas,rzg2l-usbphy-ctrl"; 60*18931afeSBiju Das reg = <0x11c40000 0x10000>; 61*18931afeSBiju Das clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 62*18931afeSBiju Das resets = <&cpg R9A07G044_USB_PRESETN>; 63*18931afeSBiju Das power-domains = <&cpg>; 64*18931afeSBiju Das #reset-cells = <1>; 65*18931afeSBiju Das }; 66