1*27dc2fb1SJoachim EastwoodNXP LPC1850 Reset Generation Unit (RGU) 2*27dc2fb1SJoachim Eastwood======================================== 3*27dc2fb1SJoachim Eastwood 4*27dc2fb1SJoachim EastwoodPlease also refer to reset.txt in this directory for common reset 5*27dc2fb1SJoachim Eastwoodcontroller binding usage. 6*27dc2fb1SJoachim Eastwood 7*27dc2fb1SJoachim EastwoodRequired properties: 8*27dc2fb1SJoachim Eastwood- compatible: Should be "nxp,lpc1850-rgu" 9*27dc2fb1SJoachim Eastwood- reg: register base and length 10*27dc2fb1SJoachim Eastwood- clocks: phandle and clock specifier to RGU clocks 11*27dc2fb1SJoachim Eastwood- clock-names: should contain "delay" and "reg" 12*27dc2fb1SJoachim Eastwood- #reset-cells: should be 1 13*27dc2fb1SJoachim Eastwood 14*27dc2fb1SJoachim EastwoodSee table below for valid peripheral reset numbers. Numbers not 15*27dc2fb1SJoachim Eastwoodin the table below are either reserved or not applicable for 16*27dc2fb1SJoachim Eastwoodnormal operation. 17*27dc2fb1SJoachim Eastwood 18*27dc2fb1SJoachim EastwoodReset Peripheral 19*27dc2fb1SJoachim Eastwood 9 System control unit (SCU) 20*27dc2fb1SJoachim Eastwood 12 ARM Cortex-M0 subsystem core (LPC43xx only) 21*27dc2fb1SJoachim Eastwood 13 CPU core 22*27dc2fb1SJoachim Eastwood 16 LCD controller 23*27dc2fb1SJoachim Eastwood 17 USB0 24*27dc2fb1SJoachim Eastwood 18 USB1 25*27dc2fb1SJoachim Eastwood 19 DMA 26*27dc2fb1SJoachim Eastwood 20 SDIO 27*27dc2fb1SJoachim Eastwood 21 External memory controller (EMC) 28*27dc2fb1SJoachim Eastwood 22 Ethernet 29*27dc2fb1SJoachim Eastwood 25 Flash bank A 30*27dc2fb1SJoachim Eastwood 27 EEPROM 31*27dc2fb1SJoachim Eastwood 28 GPIO 32*27dc2fb1SJoachim Eastwood 29 Flash bank B 33*27dc2fb1SJoachim Eastwood 32 Timer0 34*27dc2fb1SJoachim Eastwood 33 Timer1 35*27dc2fb1SJoachim Eastwood 34 Timer2 36*27dc2fb1SJoachim Eastwood 35 Timer3 37*27dc2fb1SJoachim Eastwood 36 Repetitive Interrupt timer (RIT) 38*27dc2fb1SJoachim Eastwood 37 State Configurable Timer (SCT) 39*27dc2fb1SJoachim Eastwood 38 Motor control PWM (MCPWM) 40*27dc2fb1SJoachim Eastwood 39 QEI 41*27dc2fb1SJoachim Eastwood 40 ADC0 42*27dc2fb1SJoachim Eastwood 41 ADC1 43*27dc2fb1SJoachim Eastwood 42 DAC 44*27dc2fb1SJoachim Eastwood 44 USART0 45*27dc2fb1SJoachim Eastwood 45 UART1 46*27dc2fb1SJoachim Eastwood 46 USART2 47*27dc2fb1SJoachim Eastwood 47 USART3 48*27dc2fb1SJoachim Eastwood 48 I2C0 49*27dc2fb1SJoachim Eastwood 49 I2C1 50*27dc2fb1SJoachim Eastwood 50 SSP0 51*27dc2fb1SJoachim Eastwood 51 SSP1 52*27dc2fb1SJoachim Eastwood 52 I2S0 and I2S1 53*27dc2fb1SJoachim Eastwood 53 Serial Flash Interface (SPIFI) 54*27dc2fb1SJoachim Eastwood 54 C_CAN1 55*27dc2fb1SJoachim Eastwood 55 C_CAN0 56*27dc2fb1SJoachim Eastwood 56 ARM Cortex-M0 application core (LPC4370 only) 57*27dc2fb1SJoachim Eastwood 57 SGPIO (LPC43xx only) 58*27dc2fb1SJoachim Eastwood 58 SPI (LPC43xx only) 59*27dc2fb1SJoachim Eastwood 60 ADCHS (12-bit ADC) (LPC4370 only) 60*27dc2fb1SJoachim Eastwood 61*27dc2fb1SJoachim EastwoodRefer to NXP LPC18xx or LPC43xx user manual for more details about 62*27dc2fb1SJoachim Eastwoodthe reset signals and the connected block/peripheral. 63*27dc2fb1SJoachim Eastwood 64*27dc2fb1SJoachim EastwoodReset provider example: 65*27dc2fb1SJoachim Eastwoodrgu: reset-controller@40053000 { 66*27dc2fb1SJoachim Eastwood compatible = "nxp,lpc1850-rgu"; 67*27dc2fb1SJoachim Eastwood reg = <0x40053000 0x1000>; 68*27dc2fb1SJoachim Eastwood clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; 69*27dc2fb1SJoachim Eastwood clock-names = "delay", "reg"; 70*27dc2fb1SJoachim Eastwood #reset-cells = <1>; 71*27dc2fb1SJoachim Eastwood}; 72*27dc2fb1SJoachim Eastwood 73*27dc2fb1SJoachim EastwoodReset consumer example: 74*27dc2fb1SJoachim Eastwoodmac: ethernet@40010000 { 75*27dc2fb1SJoachim Eastwood compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; 76*27dc2fb1SJoachim Eastwood reg = <0x40010000 0x2000>; 77*27dc2fb1SJoachim Eastwood interrupts = <5>; 78*27dc2fb1SJoachim Eastwood interrupt-names = "macirq"; 79*27dc2fb1SJoachim Eastwood clocks = <&ccu1 CLK_CPU_ETHERNET>; 80*27dc2fb1SJoachim Eastwood clock-names = "stmmaceth"; 81*27dc2fb1SJoachim Eastwood resets = <&rgu 22>; 82*27dc2fb1SJoachim Eastwood reset-names = "stmmaceth"; 83*27dc2fb1SJoachim Eastwood}; 84