1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: System Reset Controller on Intel Gateway SoCs
8
9maintainers:
10  - Dilip Kota <eswara.kota@linux.intel.com>
11
12properties:
13  compatible:
14    enum:
15      - intel,rcu-lgm
16      - intel,rcu-xrx200
17
18  reg:
19    description: Reset controller registers.
20    maxItems: 1
21
22  intel,global-reset:
23    description: Global reset register offset and bit offset.
24    allOf:
25      - $ref: /schemas/types.yaml#/definitions/uint32-array
26    items:
27      - description: Register offset
28      - description: Register bit offset
29        minimum: 0
30        maximum: 31
31
32  "#reset-cells":
33    minimum: 2
34    maximum: 3
35    description: |
36      First cell is reset request register offset.
37      Second cell is bit offset in reset request register.
38      Third cell is bit offset in reset status register.
39      For LGM SoC, reset cell count is 2 as bit offset in
40      reset request and reset status registers is same. Whereas
41      3 for legacy SoCs as bit offset differs.
42
43required:
44  - compatible
45  - reg
46  - intel,global-reset
47  - "#reset-cells"
48
49additionalProperties: false
50
51examples:
52  - |
53    rcu0: reset-controller@e0000000 {
54        compatible = "intel,rcu-lgm";
55        reg = <0xe0000000 0x20000>;
56        intel,global-reset = <0x10 30>;
57        #reset-cells = <2>;
58    };
59
60    pwm: pwm@e0d00000 {
61        status = "disabled";
62        compatible = "intel,lgm-pwm";
63        reg = <0xe0d00000 0x30>;
64        clocks = <&cgu0 1>;
65        #pwm-cells = <2>;
66        resets = <&rcu0 0x30 21>;
67    };
68