1 f2ad9bfdSZhen Lei# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 f2ad9bfdSZhen Lei%YAML 1.2 3 f2ad9bfdSZhen Lei--- 4 f2ad9bfdSZhen Lei$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml# 5 f2ad9bfdSZhen Lei$schema: http://devicetree.org/meta-schemas/core.yaml# 6 f2ad9bfdSZhen Lei 7 f2ad9bfdSZhen Leititle: Hisilicon System Reset Controller 8 f2ad9bfdSZhen Lei 9 f2ad9bfdSZhen Leimaintainers: 10 f2ad9bfdSZhen Lei - Wei Xu <xuwei5@hisilicon.com> 11 f2ad9bfdSZhen Lei 12 f2ad9bfdSZhen Leidescription: | 13 f2ad9bfdSZhen Lei Please also refer to reset.txt in this directory for common reset 14 f2ad9bfdSZhen Lei controller binding usage. 15 f2ad9bfdSZhen Lei The reset controller registers are part of the system-ctl block on 16 f2ad9bfdSZhen Lei hi3660 and hi3670 SoCs. 17 f2ad9bfdSZhen Lei 18 f2ad9bfdSZhen Leiproperties: 19 f2ad9bfdSZhen Lei compatible: 20 f2ad9bfdSZhen Lei oneOf: 21 f2ad9bfdSZhen Lei - items: 22 f2ad9bfdSZhen Lei - const: hisilicon,hi3660-reset 23 f2ad9bfdSZhen Lei - items: 24 f2ad9bfdSZhen Lei - const: hisilicon,hi3670-reset 25 f2ad9bfdSZhen Lei - const: hisilicon,hi3660-reset 26 f2ad9bfdSZhen Lei 27 *8362f521SDavid Heidelberg hisi,rst-syscon: 28 *8362f521SDavid Heidelberg deprecated: true 29 *8362f521SDavid Heidelberg description: phandle of the reset's syscon, use hisilicon,rst-syscon instead 30 *8362f521SDavid Heidelberg $ref: /schemas/types.yaml#/definitions/phandle 31 *8362f521SDavid Heidelberg 32 f2ad9bfdSZhen Lei hisilicon,rst-syscon: 33 f2ad9bfdSZhen Lei description: phandle of the reset's syscon. 34 f2ad9bfdSZhen Lei $ref: /schemas/types.yaml#/definitions/phandle 35 f2ad9bfdSZhen Lei 36 f2ad9bfdSZhen Lei '#reset-cells': 37 f2ad9bfdSZhen Lei description: | 38 f2ad9bfdSZhen Lei Specifies the number of cells needed to encode a reset source. 39 f2ad9bfdSZhen Lei Cell #1 : offset of the reset assert control register from the syscon 40 f2ad9bfdSZhen Lei register base 41 f2ad9bfdSZhen Lei offset + 4: deassert control register 42 f2ad9bfdSZhen Lei offset + 8: status control register 43 f2ad9bfdSZhen Lei Cell #2 : bit position of the reset in the reset control register 44 f2ad9bfdSZhen Lei const: 2 45 f2ad9bfdSZhen Lei 46 f2ad9bfdSZhen Leirequired: 47 f2ad9bfdSZhen Lei - compatible 48 f2ad9bfdSZhen Lei 49 f2ad9bfdSZhen LeiadditionalProperties: false 50 f2ad9bfdSZhen Lei 51 f2ad9bfdSZhen Leiexamples: 52 f2ad9bfdSZhen Lei - | 53 f2ad9bfdSZhen Lei #include <dt-bindings/interrupt-controller/irq.h> 54 f2ad9bfdSZhen Lei #include <dt-bindings/interrupt-controller/arm-gic.h> 55 f2ad9bfdSZhen Lei #include <dt-bindings/clock/hi3660-clock.h> 56 f2ad9bfdSZhen Lei 57 f2ad9bfdSZhen Lei iomcu: iomcu@ffd7e000 { 58 f2ad9bfdSZhen Lei compatible = "hisilicon,hi3660-iomcu", "syscon"; 59 f2ad9bfdSZhen Lei reg = <0xffd7e000 0x1000>; 60 f2ad9bfdSZhen Lei }; 61 f2ad9bfdSZhen Lei 62 f2ad9bfdSZhen Lei iomcu_rst: iomcu_rst_controller { 63 f2ad9bfdSZhen Lei compatible = "hisilicon,hi3660-reset"; 64 f2ad9bfdSZhen Lei hisilicon,rst-syscon = <&iomcu>; 65 f2ad9bfdSZhen Lei #reset-cells = <2>; 66 f2ad9bfdSZhen Lei }; 67 f2ad9bfdSZhen Lei 68 f2ad9bfdSZhen Lei /* Specifying reset lines connected to IP modules */ 69 f2ad9bfdSZhen Lei i2c@ffd71000 { 70 f2ad9bfdSZhen Lei compatible = "snps,designware-i2c"; 71 f2ad9bfdSZhen Lei reg = <0xffd71000 0x1000>; 72 f2ad9bfdSZhen Lei interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 73 f2ad9bfdSZhen Lei #address-cells = <1>; 74 f2ad9bfdSZhen Lei #size-cells = <0>; 75 f2ad9bfdSZhen Lei clock-frequency = <400000>; 76 f2ad9bfdSZhen Lei clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 77 f2ad9bfdSZhen Lei resets = <&iomcu_rst 0x20 3>; 78 f2ad9bfdSZhen Lei pinctrl-names = "default"; 79 f2ad9bfdSZhen Lei pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 80 f2ad9bfdSZhen Lei }; 81 f2ad9bfdSZhen Lei... 82