1*f2ad9bfdSZhen Lei# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*f2ad9bfdSZhen Lei%YAML 1.2
3*f2ad9bfdSZhen Lei---
4*f2ad9bfdSZhen Lei$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml#
5*f2ad9bfdSZhen Lei$schema: http://devicetree.org/meta-schemas/core.yaml#
6*f2ad9bfdSZhen Lei
7*f2ad9bfdSZhen Leititle: Hisilicon System Reset Controller
8*f2ad9bfdSZhen Lei
9*f2ad9bfdSZhen Leimaintainers:
10*f2ad9bfdSZhen Lei  - Wei Xu <xuwei5@hisilicon.com>
11*f2ad9bfdSZhen Lei
12*f2ad9bfdSZhen Leidescription: |
13*f2ad9bfdSZhen Lei  Please also refer to reset.txt in this directory for common reset
14*f2ad9bfdSZhen Lei  controller binding usage.
15*f2ad9bfdSZhen Lei  The reset controller registers are part of the system-ctl block on
16*f2ad9bfdSZhen Lei  hi3660 and hi3670 SoCs.
17*f2ad9bfdSZhen Lei
18*f2ad9bfdSZhen Leiproperties:
19*f2ad9bfdSZhen Lei  compatible:
20*f2ad9bfdSZhen Lei    oneOf:
21*f2ad9bfdSZhen Lei      - items:
22*f2ad9bfdSZhen Lei          - const: hisilicon,hi3660-reset
23*f2ad9bfdSZhen Lei      - items:
24*f2ad9bfdSZhen Lei          - const: hisilicon,hi3670-reset
25*f2ad9bfdSZhen Lei          - const: hisilicon,hi3660-reset
26*f2ad9bfdSZhen Lei
27*f2ad9bfdSZhen Lei  hisilicon,rst-syscon:
28*f2ad9bfdSZhen Lei    description: phandle of the reset's syscon.
29*f2ad9bfdSZhen Lei    $ref: /schemas/types.yaml#/definitions/phandle
30*f2ad9bfdSZhen Lei
31*f2ad9bfdSZhen Lei  '#reset-cells':
32*f2ad9bfdSZhen Lei    description: |
33*f2ad9bfdSZhen Lei      Specifies the number of cells needed to encode a reset source.
34*f2ad9bfdSZhen Lei      Cell #1 : offset of the reset assert control register from the syscon
35*f2ad9bfdSZhen Lei                register base
36*f2ad9bfdSZhen Lei                offset + 4: deassert control register
37*f2ad9bfdSZhen Lei                offset + 8: status control register
38*f2ad9bfdSZhen Lei      Cell #2 : bit position of the reset in the reset control register
39*f2ad9bfdSZhen Lei    const: 2
40*f2ad9bfdSZhen Lei
41*f2ad9bfdSZhen Leirequired:
42*f2ad9bfdSZhen Lei  - compatible
43*f2ad9bfdSZhen Lei
44*f2ad9bfdSZhen LeiadditionalProperties: false
45*f2ad9bfdSZhen Lei
46*f2ad9bfdSZhen Leiexamples:
47*f2ad9bfdSZhen Lei  - |
48*f2ad9bfdSZhen Lei    #include <dt-bindings/interrupt-controller/irq.h>
49*f2ad9bfdSZhen Lei    #include <dt-bindings/interrupt-controller/arm-gic.h>
50*f2ad9bfdSZhen Lei    #include <dt-bindings/clock/hi3660-clock.h>
51*f2ad9bfdSZhen Lei
52*f2ad9bfdSZhen Lei    iomcu: iomcu@ffd7e000 {
53*f2ad9bfdSZhen Lei        compatible = "hisilicon,hi3660-iomcu", "syscon";
54*f2ad9bfdSZhen Lei        reg = <0xffd7e000 0x1000>;
55*f2ad9bfdSZhen Lei    };
56*f2ad9bfdSZhen Lei
57*f2ad9bfdSZhen Lei    iomcu_rst: iomcu_rst_controller {
58*f2ad9bfdSZhen Lei        compatible = "hisilicon,hi3660-reset";
59*f2ad9bfdSZhen Lei        hisilicon,rst-syscon = <&iomcu>;
60*f2ad9bfdSZhen Lei        #reset-cells = <2>;
61*f2ad9bfdSZhen Lei    };
62*f2ad9bfdSZhen Lei
63*f2ad9bfdSZhen Lei    /* Specifying reset lines connected to IP modules */
64*f2ad9bfdSZhen Lei    i2c@ffd71000 {
65*f2ad9bfdSZhen Lei        compatible = "snps,designware-i2c";
66*f2ad9bfdSZhen Lei        reg = <0xffd71000 0x1000>;
67*f2ad9bfdSZhen Lei        interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
68*f2ad9bfdSZhen Lei        #address-cells = <1>;
69*f2ad9bfdSZhen Lei        #size-cells = <0>;
70*f2ad9bfdSZhen Lei        clock-frequency = <400000>;
71*f2ad9bfdSZhen Lei        clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
72*f2ad9bfdSZhen Lei        resets = <&iomcu_rst 0x20 3>;
73*f2ad9bfdSZhen Lei        pinctrl-names = "default";
74*f2ad9bfdSZhen Lei        pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
75*f2ad9bfdSZhen Lei        status = "disabled";
76*f2ad9bfdSZhen Lei    };
77*f2ad9bfdSZhen Lei...
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