1f2ad9bfdSZhen Lei# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2f2ad9bfdSZhen Lei%YAML 1.2 3f2ad9bfdSZhen Lei--- 4f2ad9bfdSZhen Lei$id: http://devicetree.org/schemas/reset/hisilicon,hi3660-reset.yaml# 5f2ad9bfdSZhen Lei$schema: http://devicetree.org/meta-schemas/core.yaml# 6f2ad9bfdSZhen Lei 7f2ad9bfdSZhen Leititle: Hisilicon System Reset Controller 8f2ad9bfdSZhen Lei 9f2ad9bfdSZhen Leimaintainers: 10f2ad9bfdSZhen Lei - Wei Xu <xuwei5@hisilicon.com> 11f2ad9bfdSZhen Lei 12f2ad9bfdSZhen Leidescription: | 13f2ad9bfdSZhen Lei Please also refer to reset.txt in this directory for common reset 14f2ad9bfdSZhen Lei controller binding usage. 15f2ad9bfdSZhen Lei The reset controller registers are part of the system-ctl block on 16f2ad9bfdSZhen Lei hi3660 and hi3670 SoCs. 17f2ad9bfdSZhen Lei 18f2ad9bfdSZhen Leiproperties: 19f2ad9bfdSZhen Lei compatible: 20f2ad9bfdSZhen Lei oneOf: 21f2ad9bfdSZhen Lei - items: 22f2ad9bfdSZhen Lei - const: hisilicon,hi3660-reset 23f2ad9bfdSZhen Lei - items: 24f2ad9bfdSZhen Lei - const: hisilicon,hi3670-reset 25f2ad9bfdSZhen Lei - const: hisilicon,hi3660-reset 26f2ad9bfdSZhen Lei 27*8362f521SDavid Heidelberg hisi,rst-syscon: 28*8362f521SDavid Heidelberg deprecated: true 29*8362f521SDavid Heidelberg description: phandle of the reset's syscon, use hisilicon,rst-syscon instead 30*8362f521SDavid Heidelberg $ref: /schemas/types.yaml#/definitions/phandle 31*8362f521SDavid Heidelberg 32f2ad9bfdSZhen Lei hisilicon,rst-syscon: 33f2ad9bfdSZhen Lei description: phandle of the reset's syscon. 34f2ad9bfdSZhen Lei $ref: /schemas/types.yaml#/definitions/phandle 35f2ad9bfdSZhen Lei 36f2ad9bfdSZhen Lei '#reset-cells': 37f2ad9bfdSZhen Lei description: | 38f2ad9bfdSZhen Lei Specifies the number of cells needed to encode a reset source. 39f2ad9bfdSZhen Lei Cell #1 : offset of the reset assert control register from the syscon 40f2ad9bfdSZhen Lei register base 41f2ad9bfdSZhen Lei offset + 4: deassert control register 42f2ad9bfdSZhen Lei offset + 8: status control register 43f2ad9bfdSZhen Lei Cell #2 : bit position of the reset in the reset control register 44f2ad9bfdSZhen Lei const: 2 45f2ad9bfdSZhen Lei 46f2ad9bfdSZhen Leirequired: 47f2ad9bfdSZhen Lei - compatible 48f2ad9bfdSZhen Lei 49f2ad9bfdSZhen LeiadditionalProperties: false 50f2ad9bfdSZhen Lei 51f2ad9bfdSZhen Leiexamples: 52f2ad9bfdSZhen Lei - | 53f2ad9bfdSZhen Lei #include <dt-bindings/interrupt-controller/irq.h> 54f2ad9bfdSZhen Lei #include <dt-bindings/interrupt-controller/arm-gic.h> 55f2ad9bfdSZhen Lei #include <dt-bindings/clock/hi3660-clock.h> 56f2ad9bfdSZhen Lei 57f2ad9bfdSZhen Lei iomcu: iomcu@ffd7e000 { 58f2ad9bfdSZhen Lei compatible = "hisilicon,hi3660-iomcu", "syscon"; 59f2ad9bfdSZhen Lei reg = <0xffd7e000 0x1000>; 60f2ad9bfdSZhen Lei }; 61f2ad9bfdSZhen Lei 62f2ad9bfdSZhen Lei iomcu_rst: iomcu_rst_controller { 63f2ad9bfdSZhen Lei compatible = "hisilicon,hi3660-reset"; 64f2ad9bfdSZhen Lei hisilicon,rst-syscon = <&iomcu>; 65f2ad9bfdSZhen Lei #reset-cells = <2>; 66f2ad9bfdSZhen Lei }; 67f2ad9bfdSZhen Lei 68f2ad9bfdSZhen Lei /* Specifying reset lines connected to IP modules */ 69f2ad9bfdSZhen Lei i2c@ffd71000 { 70f2ad9bfdSZhen Lei compatible = "snps,designware-i2c"; 71f2ad9bfdSZhen Lei reg = <0xffd71000 0x1000>; 72f2ad9bfdSZhen Lei interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 73f2ad9bfdSZhen Lei #address-cells = <1>; 74f2ad9bfdSZhen Lei #size-cells = <0>; 75f2ad9bfdSZhen Lei clock-frequency = <400000>; 76f2ad9bfdSZhen Lei clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 77f2ad9bfdSZhen Lei resets = <&iomcu_rst 0x20 3>; 78f2ad9bfdSZhen Lei pinctrl-names = "default"; 79f2ad9bfdSZhen Lei pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 80f2ad9bfdSZhen Lei }; 81f2ad9bfdSZhen Lei... 82