1*20c1b699SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*20c1b699SAnson Huang%YAML 1.2 3*20c1b699SAnson Huang--- 4*20c1b699SAnson Huang$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml# 5*20c1b699SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*20c1b699SAnson Huang 7*20c1b699SAnson Huangtitle: Freescale i.MX System Reset Controller 8*20c1b699SAnson Huang 9*20c1b699SAnson Huangmaintainers: 10*20c1b699SAnson Huang - Philipp Zabel <p.zabel@pengutronix.de> 11*20c1b699SAnson Huang 12*20c1b699SAnson Huangdescription: | 13*20c1b699SAnson Huang The system reset controller can be used to reset the GPU, VPU, 14*20c1b699SAnson Huang IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device 15*20c1b699SAnson Huang nodes should specify the reset line on the SRC in their resets 16*20c1b699SAnson Huang property, containing a phandle to the SRC device node and a 17*20c1b699SAnson Huang RESET_INDEX specifying which module to reset, as described in 18*20c1b699SAnson Huang reset.txt 19*20c1b699SAnson Huang 20*20c1b699SAnson Huang The following RESET_INDEX values are valid for i.MX5: 21*20c1b699SAnson Huang GPU_RESET 0 22*20c1b699SAnson Huang VPU_RESET 1 23*20c1b699SAnson Huang IPU1_RESET 2 24*20c1b699SAnson Huang OPEN_VG_RESET 3 25*20c1b699SAnson Huang The following additional RESET_INDEX value is valid for i.MX6: 26*20c1b699SAnson Huang IPU2_RESET 4 27*20c1b699SAnson Huang 28*20c1b699SAnson Huangproperties: 29*20c1b699SAnson Huang compatible: 30*20c1b699SAnson Huang oneOf: 31*20c1b699SAnson Huang - const: "fsl,imx51-src" 32*20c1b699SAnson Huang - items: 33*20c1b699SAnson Huang - const: "fsl,imx50-src" 34*20c1b699SAnson Huang - const: "fsl,imx51-src" 35*20c1b699SAnson Huang - items: 36*20c1b699SAnson Huang - const: "fsl,imx53-src" 37*20c1b699SAnson Huang - const: "fsl,imx51-src" 38*20c1b699SAnson Huang - items: 39*20c1b699SAnson Huang - const: "fsl,imx6q-src" 40*20c1b699SAnson Huang - const: "fsl,imx51-src" 41*20c1b699SAnson Huang - items: 42*20c1b699SAnson Huang - const: "fsl,imx6sx-src" 43*20c1b699SAnson Huang - const: "fsl,imx51-src" 44*20c1b699SAnson Huang - items: 45*20c1b699SAnson Huang - const: "fsl,imx6sl-src" 46*20c1b699SAnson Huang - const: "fsl,imx51-src" 47*20c1b699SAnson Huang - items: 48*20c1b699SAnson Huang - const: "fsl,imx6ul-src" 49*20c1b699SAnson Huang - const: "fsl,imx51-src" 50*20c1b699SAnson Huang - items: 51*20c1b699SAnson Huang - const: "fsl,imx6sll-src" 52*20c1b699SAnson Huang - const: "fsl,imx51-src" 53*20c1b699SAnson Huang 54*20c1b699SAnson Huang reg: 55*20c1b699SAnson Huang maxItems: 1 56*20c1b699SAnson Huang 57*20c1b699SAnson Huang interrupts: 58*20c1b699SAnson Huang items: 59*20c1b699SAnson Huang - description: SRC interrupt 60*20c1b699SAnson Huang - description: CPU WDOG interrupts out of SRC 61*20c1b699SAnson Huang minItems: 1 62*20c1b699SAnson Huang 63*20c1b699SAnson Huang '#reset-cells': 64*20c1b699SAnson Huang const: 1 65*20c1b699SAnson Huang 66*20c1b699SAnson Huangrequired: 67*20c1b699SAnson Huang - compatible 68*20c1b699SAnson Huang - reg 69*20c1b699SAnson Huang - interrupts 70*20c1b699SAnson Huang - '#reset-cells' 71*20c1b699SAnson Huang 72*20c1b699SAnson HuangadditionalProperties: false 73*20c1b699SAnson Huang 74*20c1b699SAnson Huangexamples: 75*20c1b699SAnson Huang - | 76*20c1b699SAnson Huang reset-controller@73fd0000 { 77*20c1b699SAnson Huang compatible = "fsl,imx51-src"; 78*20c1b699SAnson Huang reg = <0x73fd0000 0x4000>; 79*20c1b699SAnson Huang interrupts = <75>; 80*20c1b699SAnson Huang #reset-cells = <1>; 81*20c1b699SAnson Huang }; 82