1TI Keystone DSP devices 2======================= 3 4The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core 5sub-systems that are used to offload some of the processor-intensive tasks or 6algorithms, for achieving various system level goals. 7 8These processor sub-systems usually contain additional sub-modules like L1 9and/or L2 caches/SRAMs, an Interrupt Controller, an external memory controller, 10a dedicated local power/sleep controller etc. The DSP processor core in 11Keystone 2 SoCs is usually a TMS320C66x CorePac processor. 12 13DSP Device Node: 14================ 15Each DSP Core sub-system is represented as a single DT node, and should also 16have an alias with the stem 'rproc' defined. Each node has a number of required 17or optional properties that enable the OS running on the host processor (ARM 18CorePac) to perform the device management of the remote processor and to 19communicate with the remote processor. 20 21Required properties: 22-------------------- 23The following are the mandatory properties: 24 25- compatible: Should be one of the following, 26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs 27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs 28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs 29 30- reg: Should contain an entry for each value in 'reg-names'. 31 Each entry should have the memory region's start address 32 and the size of the region, the representation matching 33 the parent node's '#address-cells' and '#size-cells' values. 34 35- reg-names: Should contain strings with the following names, each 36 representing a specific internal memory region, and 37 should be defined in this order, 38 "l2sram", "l1pram", "l1dram" 39 40- clocks: Should contain the device's input clock, and should be 41 defined as per the bindings in, 42 Documentation/devicetree/bindings/clock/keystone-gate.txt 43 44- ti,syscon-dev: Should be a pair of the phandle to the Keystone Device 45 State Control node, and the register offset of the DSP 46 boot address register within that node's address space. 47 48- resets: Should contain the phandle to the reset controller node 49 managing the resets for this device, and a reset 50 specifier. Please refer to the following reset bindings 51 for the reset argument specifier as per SoC, 52 Documentation/devicetree/bindings/reset/ti-syscon-reset.txt 53 for 66AK2HK/66AK2L/66AK2E SoCs 54 55- interrupt-parent: Should contain a phandle to the Keystone 2 IRQ controller 56 IP node that is used by the ARM CorePac processor to 57 receive interrupts from the DSP remote processors. See 58 Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt 59 for details. 60 61- interrupts: Should contain an entry for each value in 'interrupt-names'. 62 Each entry should have the interrupt source number used by 63 the remote processor to the host processor. The values should 64 follow the interrupt-specifier format as dictated by the 65 'interrupt-parent' node. The purpose of each is as per the 66 description in the 'interrupt-names' property. 67 68- interrupt-names: Should contain strings with the following names, each 69 representing a specific interrupt, 70 "vring" - interrupt for virtio based IPC 71 "exception" - interrupt for exception notification 72 73- kick-gpios: Should specify the gpio device needed for the virtio IPC 74 stack. This will be used to interrupt the remote processor. 75 The gpio device to be used is as per the bindings in, 76 Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt 77 78Optional properties: 79-------------------- 80 81- memory-region: phandle to the reserved memory node to be associated 82 with the remoteproc device. The reserved memory node 83 can be a CMA memory node, and should be defined as 84 per the bindings in 85 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 86 87 88Example: 89-------- 90 /* 66AK2H/K DSP aliases */ 91 aliases { 92 rproc0 = &dsp0; 93 rproc1 = &dsp1; 94 rproc2 = &dsp2; 95 rproc3 = &dsp3; 96 rproc4 = &dsp4; 97 rproc5 = &dsp5; 98 rproc6 = &dsp6; 99 rproc7 = &dsp7; 100 }; 101 102 /* 66AK2H/K DSP memory node */ 103 reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 dsp_common_memory: dsp-common-memory@81f800000 { 109 compatible = "shared-dma-pool"; 110 reg = <0x00000008 0x1f800000 0x00000000 0x800000>; 111 reusable; 112 }; 113 }; 114 115 /* 66AK2H/K DSP node */ 116 soc { 117 dsp0: dsp@10800000 { 118 compatible = "ti,k2hk-dsp"; 119 reg = <0x10800000 0x00100000>, 120 <0x10e00000 0x00008000>, 121 <0x10f00000 0x00008000>; 122 reg-names = "l2sram", "l1pram", "l1dram"; 123 clocks = <&clkgem0>; 124 ti,syscon-dev = <&devctrl 0x40>; 125 resets = <&pscrst 0>; 126 interrupt-parent = <&kirq0>; 127 interrupts = <0 8>; 128 interrupt-names = "vring", "exception"; 129 kick-gpios = <&dspgpio0 27 0>; 130 memory-region = <&dsp_common_memory>; 131 }; 132 133 }; 134