1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI K3 R5F processor subsystems
8
9maintainers:
10  - Suman Anna <s-anna@ti.com>
11
12description: |
13  The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14  processor subsystems/clusters (R5FSS). The dual core cluster can be used
15  either in a LockStep mode providing safety/fault tolerance features or in a
16  Split mode providing two individual compute cores for doubling the compute
17  capacity on most SoCs. These are used together with other processors present
18  on the SoC to achieve various system level goals.
19
20  AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21  called "Single-CPU" mode, where only Core0 is used, but with ability to use
22  Core1's TCMs as well.
23
24  Each Dual-Core R5F sub-system is represented as a single DTS node
25  representing the cluster, with a pair of child DT nodes representing
26  the individual R5F cores. Each node has a number of required or optional
27  properties that enable the OS running on the host processor to perform
28  the device management of the remote processor and to communicate with the
29  remote processor.
30
31properties:
32  $nodename:
33    pattern: "^r5fss(@.*)?"
34
35  compatible:
36    enum:
37      - ti,am654-r5fss
38      - ti,j721e-r5fss
39      - ti,j7200-r5fss
40      - ti,am64-r5fss
41      - ti,j721s2-r5fss
42
43  power-domains:
44    description: |
45      Should contain a phandle to a PM domain provider node and an args
46      specifier containing the R5FSS device id value.
47    maxItems: 1
48
49  "#address-cells":
50    const: 1
51
52  "#size-cells":
53    const: 1
54
55  ranges:
56    description: |
57      Standard ranges definition providing address translations for
58      local R5F TCM address spaces to bus addresses.
59
60# Optional properties:
61# --------------------
62
63  ti,cluster-mode:
64    $ref: /schemas/types.yaml#/definitions/uint32
65    description: |
66      Configuration Mode for the Dual R5F cores within the R5F cluster.
67      Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
68      most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if
69      omitted; and should be either a value of 0 (Split mode) or 2
70      (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted.
71
72# R5F Processor Child Nodes:
73# ==========================
74
75patternProperties:
76  "^r5f@[a-f0-9]+$":
77    type: object
78    description: |
79      The R5F Sub-System device node should define two R5F child nodes, each
80      node representing a TI instantiation of the Arm Cortex R5F core. There
81      are some specific integration differences for the IP like the usage of
82      a Region Address Translator (RAT) for translating the larger SoC bus
83      addresses into a 32-bit address space for the processor.
84
85      Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
86      internal memories split between two banks - TCMA and TCMB (further
87      interleaved into two banks TCMB0 and TCMB1). These memories (also called
88      ATCM and BTCM) provide read/write performance on par with the core's L1
89      caches. Each of the TCMs can be enabled or disabled independently and
90      either of them can be configured to appear at that R5F's address 0x0.
91
92      The cores do not use an MMU, but has a Region Address Translater
93      (RAT) module that is accessible only from the R5Fs for providing
94      translations between 32-bit CPU addresses into larger system bus
95      addresses. Cache and memory access settings are provided through a
96      Memory Protection Unit (MPU), programmable only from the R5Fs.
97
98    allOf:
99      - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
100
101    properties:
102      compatible:
103        enum:
104          - ti,am654-r5f
105          - ti,j721e-r5f
106          - ti,j7200-r5f
107          - ti,am64-r5f
108          - ti,j721s2-r5f
109
110      reg:
111        items:
112          - description: Address and Size of the ATCM internal memory region
113          - description: Address and Size of the BTCM internal memory region
114
115      reg-names:
116        items:
117          - const: atcm
118          - const: btcm
119
120      resets:
121        description: |
122          Should contain the phandle to the reset controller node managing the
123          local resets for this device, and a reset specifier.
124        maxItems: 1
125
126      firmware-name:
127        description: |
128          Should contain the name of the default firmware image
129          file located on the firmware search path
130
131# The following properties are mandatory for R5F Core0 in both LockStep and Split
132# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
133# R5F Core1 in LockStep mode:
134
135      mboxes:
136        description: |
137          OMAP Mailbox specifier denoting the sub-mailbox, to be used for
138          communication with the remote processor. This property should match
139          with the sub-mailbox node used in the firmware image.
140        maxItems: 1
141
142      memory-region:
143        description: |
144          phandle to the reserved memory nodes to be associated with the
145          remoteproc device. There should be at least two reserved memory nodes
146          defined. The reserved memory nodes should be carveout nodes, and
147          should be defined with a "no-map" property as per the bindings in
148          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
149        minItems: 2
150        maxItems: 8
151        items:
152          - description: region used for dynamic DMA allocations like vrings and
153                         vring buffers
154          - description: region reserved for firmware image sections
155        additionalItems: true
156
157
158# Optional properties:
159# --------------------
160# The following properties are optional properties for each of the R5F cores:
161
162      ti,atcm-enable:
163        $ref: /schemas/types.yaml#/definitions/uint32
164        enum: [0, 1]
165        description: |
166          R5F core configuration mode dictating if ATCM should be enabled. The
167          R5F address of ATCM is dictated by ti,loczrama property. Should be
168          either a value of 1 (enabled) or 0 (disabled), default is disabled
169          if omitted. Recommended to enable it for maximizing TCMs.
170
171      ti,btcm-enable:
172        $ref: /schemas/types.yaml#/definitions/uint32
173        enum: [0, 1]
174        description: |
175          R5F core configuration mode dictating if BTCM should be enabled. The
176          R5F address of BTCM is dictated by ti,loczrama property. Should be
177          either a value of 1 (enabled) or 0 (disabled), default is enabled if
178          omitted.
179
180      ti,loczrama:
181        $ref: /schemas/types.yaml#/definitions/uint32
182        enum: [0, 1]
183        description: |
184          R5F core configuration mode dictating which TCM should appear at
185          address 0 (from core's view). Should be either a value of 1 (ATCM
186          at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
187
188      sram:
189        $ref: /schemas/types.yaml#/definitions/phandle-array
190        minItems: 1
191        maxItems: 4
192        description: |
193          phandles to one or more reserved on-chip SRAM regions. The regions
194          should be defined as child nodes of the respective SRAM node, and
195          should be defined as per the generic bindings in,
196          Documentation/devicetree/bindings/sram/sram.yaml
197
198    required:
199      - compatible
200      - reg
201      - reg-names
202      - ti,sci
203      - ti,sci-dev-id
204      - ti,sci-proc-ids
205      - resets
206      - firmware-name
207
208    unevaluatedProperties: false
209
210if:
211  properties:
212    compatible:
213      enum:
214        - ti,am64-r5fss
215then:
216  properties:
217    ti,cluster-mode:
218      enum: [0, 2]
219else:
220  properties:
221    ti,cluster-mode:
222      enum: [0, 1]
223
224required:
225  - compatible
226  - power-domains
227  - "#address-cells"
228  - "#size-cells"
229  - ranges
230
231additionalProperties: false
232
233examples:
234  - |
235    soc {
236        #address-cells = <2>;
237        #size-cells = <2>;
238
239        bus@100000 {
240            compatible = "simple-bus";
241            #address-cells = <2>;
242            #size-cells = <2>;
243            ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
244                     <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
245                     <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
246                     <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
247
248            bus@28380000 {
249                compatible = "simple-bus";
250                #address-cells = <2>;
251                #size-cells = <2>;
252                ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
253                         <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
254                         <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
255                         <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
256
257                /* AM65x MCU R5FSS node */
258                mcu_r5fss0: r5fss@41000000 {
259                    compatible = "ti,am654-r5fss";
260                    power-domains = <&k3_pds 129>;
261                    ti,cluster-mode = <1>;
262                    #address-cells = <1>;
263                    #size-cells = <1>;
264                    ranges = <0x41000000 0x00 0x41000000 0x20000>,
265                             <0x41400000 0x00 0x41400000 0x20000>;
266
267                    mcu_r5f0: r5f@41000000 {
268                        compatible = "ti,am654-r5f";
269                        reg = <0x41000000 0x00008000>,
270                              <0x41010000 0x00008000>;
271                        reg-names = "atcm", "btcm";
272                        ti,sci = <&dmsc>;
273                        ti,sci-dev-id = <159>;
274                        ti,sci-proc-ids = <0x01 0xFF>;
275                        resets = <&k3_reset 159 1>;
276                        firmware-name = "am65x-mcu-r5f0_0-fw";
277                        ti,atcm-enable = <1>;
278                        ti,btcm-enable = <1>;
279                        ti,loczrama = <1>;
280                        mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
281                        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
282                                        <&mcu_r5fss0_core0_memory_region>;
283                        sram = <&mcu_r5fss0_core0_sram>;
284                    };
285
286                    mcu_r5f1: r5f@41400000 {
287                        compatible = "ti,am654-r5f";
288                        reg = <0x41400000 0x00008000>,
289                              <0x41410000 0x00008000>;
290                        reg-names = "atcm", "btcm";
291                        ti,sci = <&dmsc>;
292                        ti,sci-dev-id = <245>;
293                        ti,sci-proc-ids = <0x02 0xFF>;
294                        resets = <&k3_reset 245 1>;
295                        firmware-name = "am65x-mcu-r5f0_1-fw";
296                        ti,atcm-enable = <1>;
297                        ti,btcm-enable = <1>;
298                        ti,loczrama = <1>;
299                        mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
300                    };
301                };
302            };
303        };
304    };
305