1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI K3 R5F processor subsystems
8
9maintainers:
10  - Suman Anna <s-anna@ti.com>
11
12description: |
13  The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14  processor subsystems/clusters (R5FSS). The dual core cluster can be used
15  either in a LockStep mode providing safety/fault tolerance features or in a
16  Split mode providing two individual compute cores for doubling the compute
17  capacity on most SoCs. These are used together with other processors present
18  on the SoC to achieve various system level goals.
19
20  AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21  called "Single-CPU" mode, where only Core0 is used, but with ability to use
22  Core1's TCMs as well.
23
24  Each Dual-Core R5F sub-system is represented as a single DTS node
25  representing the cluster, with a pair of child DT nodes representing
26  the individual R5F cores. Each node has a number of required or optional
27  properties that enable the OS running on the host processor to perform
28  the device management of the remote processor and to communicate with the
29  remote processor.
30
31properties:
32  $nodename:
33    pattern: "^r5fss(@.*)?"
34
35  compatible:
36    enum:
37      - ti,am654-r5fss
38      - ti,j721e-r5fss
39      - ti,j7200-r5fss
40      - ti,am64-r5fss
41
42  power-domains:
43    description: |
44      Should contain a phandle to a PM domain provider node and an args
45      specifier containing the R5FSS device id value.
46    maxItems: 1
47
48  "#address-cells":
49    const: 1
50
51  "#size-cells":
52    const: 1
53
54  ranges:
55    description: |
56      Standard ranges definition providing address translations for
57      local R5F TCM address spaces to bus addresses.
58
59# Optional properties:
60# --------------------
61
62  ti,cluster-mode:
63    $ref: /schemas/types.yaml#/definitions/uint32
64    description: |
65      Configuration Mode for the Dual R5F cores within the R5F cluster.
66      Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
67      most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;
68      and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)
69      on AM64x SoCs, default is Split mode if omitted.
70
71# R5F Processor Child Nodes:
72# ==========================
73
74patternProperties:
75  "^r5f@[a-f0-9]+$":
76    type: object
77    description: |
78      The R5F Sub-System device node should define two R5F child nodes, each
79      node representing a TI instantiation of the Arm Cortex R5F core. There
80      are some specific integration differences for the IP like the usage of
81      a Region Address Translator (RAT) for translating the larger SoC bus
82      addresses into a 32-bit address space for the processor.
83
84      Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
85      internal memories split between two banks - TCMA and TCMB (further
86      interleaved into two banks TCMB0 and TCMB1). These memories (also called
87      ATCM and BTCM) provide read/write performance on par with the core's L1
88      caches. Each of the TCMs can be enabled or disabled independently and
89      either of them can be configured to appear at that R5F's address 0x0.
90
91      The cores do not use an MMU, but has a Region Address Translater
92      (RAT) module that is accessible only from the R5Fs for providing
93      translations between 32-bit CPU addresses into larger system bus
94      addresses. Cache and memory access settings are provided through a
95      Memory Protection Unit (MPU), programmable only from the R5Fs.
96
97    allOf:
98      - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
99
100    properties:
101      compatible:
102        enum:
103          - ti,am654-r5f
104          - ti,j721e-r5f
105          - ti,j7200-r5f
106          - ti,am64-r5f
107
108      reg:
109        items:
110          - description: Address and Size of the ATCM internal memory region
111          - description: Address and Size of the BTCM internal memory region
112
113      reg-names:
114        items:
115          - const: atcm
116          - const: btcm
117
118      resets:
119        description: |
120          Should contain the phandle to the reset controller node managing the
121          local resets for this device, and a reset specifier.
122        maxItems: 1
123
124      firmware-name:
125        description: |
126          Should contain the name of the default firmware image
127          file located on the firmware search path
128
129# The following properties are mandatory for R5F Core0 in both LockStep and Split
130# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
131# R5F Core1 in LockStep mode:
132
133      mboxes:
134        description: |
135          OMAP Mailbox specifier denoting the sub-mailbox, to be used for
136          communication with the remote processor. This property should match
137          with the sub-mailbox node used in the firmware image.
138        maxItems: 1
139
140      memory-region:
141        description: |
142          phandle to the reserved memory nodes to be associated with the
143          remoteproc device. There should be at least two reserved memory nodes
144          defined. The reserved memory nodes should be carveout nodes, and
145          should be defined with a "no-map" property as per the bindings in
146          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
147        minItems: 2
148        maxItems: 8
149        items:
150          - description: region used for dynamic DMA allocations like vrings and
151                         vring buffers
152          - description: region reserved for firmware image sections
153        additionalItems: true
154
155
156# Optional properties:
157# --------------------
158# The following properties are optional properties for each of the R5F cores:
159
160      ti,atcm-enable:
161        $ref: /schemas/types.yaml#/definitions/uint32
162        enum: [0, 1]
163        description: |
164          R5F core configuration mode dictating if ATCM should be enabled. The
165          R5F address of ATCM is dictated by ti,loczrama property. Should be
166          either a value of 1 (enabled) or 0 (disabled), default is disabled
167          if omitted. Recommended to enable it for maximizing TCMs.
168
169      ti,btcm-enable:
170        $ref: /schemas/types.yaml#/definitions/uint32
171        enum: [0, 1]
172        description: |
173          R5F core configuration mode dictating if BTCM should be enabled. The
174          R5F address of BTCM is dictated by ti,loczrama property. Should be
175          either a value of 1 (enabled) or 0 (disabled), default is enabled if
176          omitted.
177
178      ti,loczrama:
179        $ref: /schemas/types.yaml#/definitions/uint32
180        enum: [0, 1]
181        description: |
182          R5F core configuration mode dictating which TCM should appear at
183          address 0 (from core's view). Should be either a value of 1 (ATCM
184          at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
185
186      sram:
187        $ref: /schemas/types.yaml#/definitions/phandle-array
188        minItems: 1
189        maxItems: 4
190        description: |
191          phandles to one or more reserved on-chip SRAM regions. The regions
192          should be defined as child nodes of the respective SRAM node, and
193          should be defined as per the generic bindings in,
194          Documentation/devicetree/bindings/sram/sram.yaml
195
196    required:
197      - compatible
198      - reg
199      - reg-names
200      - ti,sci
201      - ti,sci-dev-id
202      - ti,sci-proc-ids
203      - resets
204      - firmware-name
205
206    unevaluatedProperties: false
207
208if:
209  properties:
210    compatible:
211      enum:
212        - ti,am64-r5fss
213then:
214  properties:
215    ti,cluster-mode:
216      enum: [0, 2]
217else:
218  properties:
219    ti,cluster-mode:
220      enum: [0, 1]
221
222required:
223  - compatible
224  - power-domains
225  - "#address-cells"
226  - "#size-cells"
227  - ranges
228
229additionalProperties: false
230
231examples:
232  - |
233    / {
234        model = "Texas Instruments K3 AM654 SoC";
235        compatible = "ti,am654-evm", "ti,am654";
236        #address-cells = <2>;
237        #size-cells = <2>;
238
239        bus@100000 {
240            compatible = "simple-bus";
241            #address-cells = <2>;
242            #size-cells = <2>;
243            ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
244                     <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
245                     <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
246                     <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
247
248            bus@28380000 {
249                compatible = "simple-bus";
250                #address-cells = <2>;
251                #size-cells = <2>;
252                ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
253                         <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
254                         <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
255                         <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
256
257                /* AM65x MCU R5FSS node */
258                mcu_r5fss0: r5fss@41000000 {
259                    compatible = "ti,am654-r5fss";
260                    power-domains = <&k3_pds 129>;
261                    ti,cluster-mode = <1>;
262                    #address-cells = <1>;
263                    #size-cells = <1>;
264                    ranges = <0x41000000 0x00 0x41000000 0x20000>,
265                             <0x41400000 0x00 0x41400000 0x20000>;
266
267                    mcu_r5f0: r5f@41000000 {
268                        compatible = "ti,am654-r5f";
269                        reg = <0x41000000 0x00008000>,
270                              <0x41010000 0x00008000>;
271                        reg-names = "atcm", "btcm";
272                        ti,sci = <&dmsc>;
273                        ti,sci-dev-id = <159>;
274                        ti,sci-proc-ids = <0x01 0xFF>;
275                        resets = <&k3_reset 159 1>;
276                        firmware-name = "am65x-mcu-r5f0_0-fw";
277                        ti,atcm-enable = <1>;
278                        ti,btcm-enable = <1>;
279                        ti,loczrama = <1>;
280                        mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
281                        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
282                                        <&mcu_r5fss0_core0_memory_region>;
283                        sram = <&mcu_r5fss0_core0_sram>;
284                    };
285
286                    mcu_r5f1: r5f@41400000 {
287                        compatible = "ti,am654-r5f";
288                        reg = <0x41400000 0x00008000>,
289                              <0x41410000 0x00008000>;
290                        reg-names = "atcm", "btcm";
291                        ti,sci = <&dmsc>;
292                        ti,sci-dev-id = <245>;
293                        ti,sci-proc-ids = <0x02 0xFF>;
294                        resets = <&k3_reset 245 1>;
295                        firmware-name = "am65x-mcu-r5f0_1-fw";
296                        ti,atcm-enable = <1>;
297                        ti,btcm-enable = <1>;
298                        ti,loczrama = <1>;
299                        mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
300                    };
301                };
302            };
303        };
304    };
305